| 1 | 3.2Gb/s memory transmitter with pre-emphasis and crosstalk compensation scheme = 프리엠파시스 회로와 크로스톡 보완 구조를 포함하는 3.2Gb/s 메모리 트랜스미터link Huh, Lynn; 허린; et al, 한국과학기술원, 2007 |
| 2 | Active-mode and autonomous power gating circuits : synthesis and design considerations = Active 모드 파워 게이팅과 autonomous 파워 게이팅 : 합성 및 디자인 고려사항link Seomun, Jun; 서문준; et al, 한국과학기술원, 2011 |
| 3 | Analysis and minimization of power in mesh clock network = 메시 클락 네트워크에서의 파워 분석과 최소화link Mo, Min-Young; 모민영; et al, 한국과학기술원, 2013 |
| 4 | Clock Gating Synthesis of Pulsed-Latch Circuits Paik, Seung-Whun; Han, In-Hak; Kim, Sang-Min; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.7, pp.1019 - 1030, 2012-07 |
| 5 | Clock gating synthesis through reusing existing combinational logic = 논리 회로의 재활용을 이용한 클락게이팅의 합성link Han, In-Hak; 한인학; et al, 한국과학기술원, 2012 |
| 6 | Clock mesh design for multi-level clock gating = 다계층 클락 게이팅이 적용된 회로를 위한 클락 메쉬의 설계link Lee, Dong-Soo; 이동수; et al, 한국과학기술원, 2014 |
| 7 | Design and Optimization of Power-Gated Circuits With Autonomous Data Retention Seomun, Jun; Shin, Young-Soo, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.2, pp.227 - 236, 2011-02 |
| 8 | Dual-$V_t$ Allocation with Constraint on Minimum Ion Implantation Width = 이온 임플란트의 최소 너비를 고려한 Dual $V_t$ 할당 기법link Lee, Yoo-Jong; 이유종; et al, 한국과학기술원, 2014 |
| 9 | Energy-efficient design for timing-approximate computing = 시간 근사 컴퓨팅을 위한 에너지 효율적 설계link Ahn, Yong-Soo; 안용수; et al, 한국과학기술원, 2014 |
| 10 | HLS-1: A High-Level Synthesis Framework for Latch-Based Architectures Paik, Seung-Whun; Shin, In-Sup; Kim, Tae-Whan; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.29, pp.657 - 670, 2010-05 |
| 11 | HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures Shin, In-Sup; Paik, Seung-Whun; Shin, Dong-Wan; Shin, Young-Soo, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.4, pp.593 - 604, 2012-04 |
| 12 | HLS-dv: High-level synthesis of dual-$V_{dd}$ architectures = 이중 전압을 이용한 아키텍처의 상위 수준 합성link Shin, In-Sup; 신인섭; et al, 한국과학기술원, 2009 |
| 13 | Integrated design flow for pulsed latch ASIC circuits = 펄스래치 회로를 위한 디자인 플로우link Kim, Duck-Hwan; 김덕환; et al, 한국과학기술원, 2012 |
| 14 | Low voltage design of pipeline architecture through one-cycle correction of timing errors = 단일 사이클 페널티를 갖는 타이밍 오류 정정 기법을 이용한 저전압 파이프라인 아키텍처 설계link Shin, In-Sub; 신인섭; et al, 한국과학기술원, 2014 |
| 15 | Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating Kim, Nam-Sung; Sinkar, Abhishek; Seomun, Jun; Shin, Young-Soo, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.10, pp.1885 - 1890, 2012-10 |
| 16 | Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping = 플립플랍 비대칭화와 테크놀로지 매핑을 통한 순차회로의 누설전류 감소link Heo, Se-Wan; 허세완; et al, 한국과학기술원, 2007 |
| 17 | Minimizing wakeup latency under rush-current constraint in power-gated circuits = 파워 게이팅이 적용된 회로에서 제한된 돌입 전류를 사용한 활성화 시간 최적화 기법link Kim, Sang-Min; 김상민; et al, 한국과학기술원, 2010 |
| 18 | Power Gating: Circuits, Design Methodologies, and Best Practice for Standard-Cell VLSI Designs Shin, Young-Soo; Seomun, Jun; Choi, Kyu-Myung; Sakurai, Takayasu, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.15, no.4, 2010-09 |
| 19 | Pulse width allocation and clock skew scheduling : Optimizing sequential circuits based on pulsed latches = 펄스 폭 할당 및 클락 스큐 스케쥴링을 이용한 펄스 래치 순차 회로의 최적화 기법link Lee, Hye-In; 이혜인; et al, 한국과학기술원, 2009 |
| 20 | Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches Lee, Hye-In; Paik, Seung-Whun; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.29, no.3, pp.355 - 366, 2010-03 |
| 21 | Pulsed-Latch Circuits: A New Dimension in ASIC Design Shin, Young-Soo; Paik, Seung-Whun, IEEE DESIGN TEST OF COMPUTERS, v.28, pp.50 - 57, 2011 |
| 22 | Pulsed-Latch-Based ASIC design for high performance and low power = 펄스래치기반 고성능 저전력 ASIC 설계link Paik, Seung-Whun; 백승훈; et al, 한국과학기술원, 2011 |
| 23 | Retiming pulsed-latch circuits for high-performance ASIC designs = 고성능 ASIC 디자인을 위한 펄스 래치 회로 리타이밍 기법link Lee, Seong-Gwan; 이성관; et al, 한국과학기술원, 2010 |
| 24 | Retiming Pulsed-Latch Circuits with Regulating Pulse Width Paik, Seung-Whun; Lee, Seong-Gwan; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.8, pp.1114 - 1127, 2011-08 |
| 25 | SAMPLING CORRELATION SOURCES FOR TIMING YIELD ANALYSIS OF SEQUENTIAL CIRCUITS WITH CLOCK NETWORKS Yu, Lee-Eun; Shin, Chang-Sik; Paik, Seung-Whun; Liou, Jing-Jia; Shin, Young-Soo, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.20, no.8, pp.1547 - 1569, 2011-12 |
| 26 | Semicustom design methodology for power gated circuits for low leakage applications = 낮은 누설 전류를 갖는 응용을 위한 파워 게이팅 회로의 세미커스텀 설계 방법link Kim, Hyung-Ock; 김형옥; et al, 한국과학기술원, 2009 |
| 27 | Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements Shin, Young-Soo; Paik, Seung-Whun; Kim, Hyung-Ock, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.28, no.3, pp.327 - 339, 2009-03 |
| 28 | Skewed Flip-Flop and Mixed-V-t Gates for Minimizing Leakage in Sequential Circuits Seomun, Jun; Kim, Jae-Hyun; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.27, pp.1956 - 1968, 2008-11 |
| 29 | Skewed flip-flop transformation for minimizing leakage in sequential circuits = 순차 회로의 누설 전류를 줄이기 위한 비대칭 플립 플롭 변환link Seomun, Jun; 서문, 준; et al, 한국과학기술원, 2007 |
| 30 | Structured ASIC design methodology using selectively patterned masks = 선택적 부분 패터닝을 이용한 스트럭처드 ASIC 설계 방법link Baek, Don-Kyu; 백돈규; et al, 한국과학기술원, 2011 |
| 31 | Structured ASIC design methodology using selectively patterned masks = 선택적 부분 패터닝을 이용한 스트럭처드 ASIC 설계 방법link Baek, Don-Kyu; 백돈규; et al, 한국과학기술원, 2011 |
| 32 | Synthesis of Active-Mode Power-Gating Circuits Seomun, Jun; Shin, In-Sup; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.3, pp.391 - 403, 2012-03 |
| 33 | Technology mapping for morphed regular architecture = MRA를 위한 테크놀로지 매핑link Moon, Young-Suk; 문영석; et al, 한국과학기술원, 2009 |
| 34 | Thermal Signature: An Accurate and Fast Thermal Model = Thermal Signature: 정확하고 빠른 온도 지표link Kung, Jae-Ha; 궁재하; et al, 한국과학기술원, 2012 |
| 35 | Thermal-aware time budgeting for hierarchical VLSI designs = 온도를 고려한 계층적 VLSI 설계의 시간 분배 기법link Jung, Min-Wook; 정민욱; et al, 한국과학기술원, 2010 |
| 36 | Timing analysis and optimization of sequential circuits with dual-edge-triggered flip-flops = 듀얼-에지-구동 플립플랍을 이용한 순차 회로의 타이밍 분석과 최적화link Oh, Chung-Ki; 오충기; et al, 한국과학기술원, 2009 |
| 37 | Timing yield analysis of sequential circuits considering clock network = 클락 네트워크를 고려한 순차 회로의 타이밍 수율 분석link Shin, Chang-Sik; 신창식; et al, 한국과학기술원, 2009 |
