Thermal-aware time budgeting for hierarchical VLSI designs

Abstract

Time budgeting, which generates timing assertion at block boundaries in hierarchical VLSI designs, determines leakage power consumption of overall design, since the timing assertion from time budgeting step dictates the proportion of $high-V_t$ and $low-V_t$ gates of each block. Active leakage power is much larger (~10X) than standby leakage power, and exponentially depends on temperature. Therefore, it is essential to consider thermal influence on leakage in time budgeting to reduce active leakage power effectively in hierarchical designs. In this thesis, weighted bounded potential slack that takes account of thermal influence on leakage is introduced as a measure of active leakage power, and is experimentally shown to be highly correlated with active leakage power. Thermal-aware time budgeting was formulated as linear programming with objective of weighted bounded potential slack. In experiments with example hierarchical designs implemented in 45-nm commercial technology, we confirmed that thermal-aware time budgeting was able to reduce active leakage power by 16.8% on average compared to conventional time budgeting, when both are followed by the same $dual-V_t$ allocation.