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Shin, Youngsoo (신영수)
교수, School of Electrical Engineering(전기및전자공학부)

http://dtlab.kaist.ac.kr/

Research Area
VLSI CAD, Low-power, DFM (Design for Manufacturability), Computational Lithography, Neuromorphic circuit
Co-researchers
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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    Computational lithography using machine learning models

    Shin, Youngsooresearcher, IPSJ Transactions on System LSI Design Methodology, v.14, pp.2 - 10, 2021-02

    2
    Layout Pattern Synthesis for Lithography Optimizations

    Kareem, Pervaiz; Kwon, Yonghwi; Shin, Youngsooresearcher, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.33, no.2, pp.283 - 290, 2020-05

    3
    Selective use of stitch-induced via for V0 mask reduction: standard cell design and placement optimization

    Hyun, Dai Joon; Jung, Younggwang; Shin, Youngsooresearcher, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E102.A, no.12, pp.1711 - 1719, 2019-12

    4
    Cut optimization for redundant via insertion in self-aligned double patterning

    Song, Youngsoo; Hyun, Daijoon; Lee, Jingon; et al, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.24, no.6, pp.61:1 - 61:21, 2019-09

    5
    Neural network classifier-based OPC with imbalanced training data

    Choi, Suhyeong; Shim, Seongbo; Shin, Youngsooresearcher, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.38, no.5, pp.938 - 948, 2019-05

    6
    Integrated latch placement and cloning for timing optimization

    Jung, Jinwook; Nam, Gi-Joon; Chung, Woohyun; et al, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.24, no.2, pp.22:1 - 22:17, 2019-03

    7
    Integrated approach of airgap insertion for circuit timing optimization

    Hyun, Daijoon; Shin, Youngsooresearcher, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.24, no.2, pp.24:1 - 24:22, 2019-03

    8
    OWARU: free space-aware timing-driven incremental placement with critical path smoothing

    Jung, Jinwook; Nam, Gijoon; Reddy, Lakshmi; et al, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.37, no.9, pp.1825 - 1838, 2018-09

    9
    Electrothermal Analysis With Nonconvective Boundary Conditions

    Choi, Suhyeong; Shim, Seongbo; Shin, Youngsooresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.8, pp.1044 - 1048, 2018-08

    10
    Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops

    Han, Inhak; Shin, Youngsooresearcher, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.23, no.5, pp.61:1 - 61:21, 2018-08

    11
    Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

    Shin, Youngsooresearcher, IEEE DESIGN & TEST, v.35, no.3, pp.100 - 101, 2018-05

    12
    Memory-efficient parametric semi-global matching

    Lee, Yeong Min; Park, Min Gyu; Hwang, Youngbae; et al, IEEE SIGNAL PROCESSING LETTERS, v.25, no.2, pp.194 - 198, 2018-02

    13
    Module grouping to reduce the area of test wrappers in SoCs

    Kim, Sang-Min; Shin, Youngsooresearcher, INTEGRATION-THE VLSI JOURNAL, v.60, pp.39 - 47, 2018-01

    14
    Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography

    Shim, Seongbo; Shin, Youngsooresearcher, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.36, no.9, pp.1522 - 1531, 2017-09

    15
    Machine Learning-Guided Etch Proximity Correction

    Shim, Seongbo; Shin, Youngsooresearcher, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.30, no.1, pp.1 - 7, 2017-02

    16
    Lithography Defect Probability and Its Application to Physical Design Optimization

    Shim, Seongbo; Chung, Woohyun; Shin, Youngsooresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.271 - 285, 2017-01

    17
    Reliable Memristive Switching Memory Devices Enabled by Densely Packed Silver Nanocone Arrays as Electric -Field Concentrators

    You, Byoung Kuk; Kim, Jong Min; Joe, Daniel J.; et al, ACS NANO, v.10, no.10, pp.9478 - 9488, 2016-10

    18
    Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization

    Kim, Sangmin; Kang, Seokhyeong; Shin, Youngsooresearcher, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.21, no.3, 2016-07

    19
    Wakeup scheduling and its buffered tree synthesis for power gating circuits

    Kim, Sangmin; Paik, Seungwhun; Kang, Seokhyeong; et al, INTEGRATION-THE VLSI JOURNAL, v.53, pp.157 - 170, 2016-03

    20
    One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements

    Shin, Insup; Kim, Jae Joon; Lin, Yu Shiang; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.600 - 612, 2016-02
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