Power Gating: Circuits, Design Methodologies, and Best Practice for Standard-Cell VLSI Designs

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Power gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.
Publisher
ASSOC COMPUTING MACHINERY
Issue Date
2010-09
Language
English
Article Type
Article
Keywords

LEAKAGE CURRENT; CMOS CIRCUITS; BODY BIAS; SEMICUSTOM DESIGN; GATED CIRCUITS; SUPPLY-VOLTAGE; FLIP-FLOP; REDUCTION; SCHEME; MICROPROCESSORS

Citation

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.15, no.4

ISSN
1084-4309
DOI
10.1145/1835420.1835421
URI
http://hdl.handle.net/10203/99302
Appears in Collection
EE-Journal Papers(저널논문)
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