Active-mode and autonomous power gating circuits : synthesis and design considerations = Active 모드 파워 게이팅과 autonomous 파워 게이팅 : 합성 및 디자인 고려사항 synthesis and design considerations

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Power gating has become one of the most widely used circuit design techniques for reducing leakage current. Power gating is conceptually very simple; it cuts off a circuit from its power and/or ground by means of current switches when the circuit is expected to be in idle state for a long time. Implementation of power gating with standard-cell, however, is not simple, and it requires many design consideration. The considerations are current switch design and sizing, data retention, physical design, and so on. The design methodologies of power gating have been heavily investigated and improved, but it still has some drawbacks such as wiring overhead for data retention. Moreover, conventional power gating cannot reduce active leakage, which becomes more important for low power design as technology scales down. In this thesis, we introduce two advanced power gating circuits to overcome such limitations of power gating, and propose the design methods of these circuits. Active mode power gating (AMPG) has been recently proposed as a run time technique to suppress active leakage, which can complement design time techniques. It applies power gating on parts of circuits that are only responsible for computing the inputs of clock-gated flip-flops, and makes clock gating signals to control power gating. Synthesis problem of AMPG is to select the parts of circuits (sets of gates) to be power gated and to decide the size of current switches to be attached to them. We identify four constraints to solve this problem, namely energy, functional, timing, and current constraints, and then propose synthesis algorithm. Power network of each set of gates has to be isolated from one another, because they can exist in different states, either on- or off-states, following the independent clock gating signals. We also propose a placement algorithm that separately places each set of gates, while at the same time clustering the gates in same sets to avoid the excessive consumption of w...
Shin, Young-Sooresearcher신영수researcher
한국과학기술원 : 전기 및 전자공학과,
Issue Date
466446/325007  / 020075085

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2011.2, [ xii, 125 p. ]


active leakage; autonomous power gating; active-mode power gating; Power gating; self-data retention; self 데이터 리텐션; active 누설 전류; Autonomous 파워 게이팅; Active 모드 파워 게이팅; 파워 게이팅

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