3.2Gb/s memory transmitter with pre-emphasis and crosstalk compensation scheme

Abstract

Increasing on-die bandwidth has created a growing demand for faster off-chip links. Besides enhancing the data rates of individual links, dense communication environment is required to accommodate high aggregate throughput; the augmentation of the amount of data has induced routings on PCB to be more complex and dense. Under these circumstances, channels have become more susceptible to energy coupling caused by the neighboring channels, which is called crosstalk. There are two types of distortion resulting from crosstalk: amplitude distortion and timing jitter. These distortions cause serious impairments on data. However, recent works of crosstalk cancellation mostly focus only on the compensation of amplitude distortion. This thesis presents the design of a transmitter with a new crosstalk compensation scheme. The proposed scheme detects the crosstalk mode of two neighboring channels by comparing their signal patterns. Among five crosstalk modes, even and odd modes are responsible for timing distortion, and superposition modes are responsible for amplitude distortion. According to the mode information, the proposed compensator provides the appropriate compensation. Since the proposed compensator composed of both phase compensator and glitch canceller, the crosstalk can be effectively reduced. The efficiency of the transmitter is demonstrated by transmitting a 3.2Gb/s data over 4-inch FR4 channel. The proposed transmitter is designed in 0.18um CMOS process. The peak-to-peak jitter of transmitted data is simulated as 106-ps.