Browse "School of Electrical Engineering(전기및전자공학부)" by Author Hur, Jae
Showing results 1 to 45 of 45
| A Comparative Study on Hot-Carrier Injection in 5-story Vertically Integrated Inversion-Mode and Junctionless-Mode Gate-All-Around MOSFETs Kim, Seong-Yeon; Lee, Byung-Hyun; Hur, Jae; Park, Jun-Young; Jeon, Seung-Bae; Lee, Seung-Wook; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.39, no.1, pp.4 - 7, 2018-01 |
| A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain Lee, Seung-Wook; Kim, Seong-Yeon; Hwang, Kyu-Man; Jin, Ik Kyeong; Hur, Jae; Kim, Dohyun; Son, Jun Woo; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.11, pp.5208 - 5212, 2018-11 |
| A Core Compact Model for Multiple-Gate Junctionless FETs Hur, Jae; Moon, Dong-Il; Choi, Ji-Min; Seol, Myeong-Lok; Jeong, Ui-Sik; Jeon, Chang-Hoon; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.62, no.7, pp.2285 - 2291, 2015-07 |
A frequency reconfigurable dipole antenna with solid-state plasma in silicon Kim, Da-Jin; Jo, Eon-Seok; Cho, Young-Kyun; Hur, Jae; Kim, Choong-Ki; Kim, Cheol Ho; Park, Bonghyuk; et al, SCIENTIFIC REPORTS, v.8, 2018-10 |
| A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure Hur, Jae; Choi, Ji-Min; Woo, Jong-Ho; Jang, Hyunjae; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.62, no.9, pp.2710 - 2716, 2015-09 |
| A Recoverable Synapse Device Using a Three-Dimensional Silicon Transistor Hur, Jae; Jang, Byung Chul; Park, Jihun; Moon, Dong-Il; Bae, Hagyoul; Park, Jun-Young; Kim, Gun-Hee; et al, ADVANCED FUNCTIONAL MATERIALS, v.28, no.47, 2018-11 |
| A Steep-Slope Phenomenon by Gate Charge Pumping in a MOSFET Kim, Myung-Su; Yun, Gyeong-Jun; Kim, Wu-Kang; Seo, Myungsoo; Kim, Da-Jin; Yu, Ji-Man; Han, Joon-Kyu; et al, IEEE ELECTRON DEVICE LETTERS, v.43, no.4, pp.521 - 524, 2022-04 |
| A Strategy for Optimizing Low Operating Voltage in a Silicon Biristor Son, Jun-Woo; Hur, Jae; Kim, Wu-Kang; Lee, Geon-Beom; Choi, Yang-Kyu, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.19, pp.5 - 10, 2020-01 |
| A Study of High-Temperature Effects on an Asymmetrically Doped Vertical Pillar-Type Field-Effect Transistor Han, Joon-Kyu; Hur, Jae; Kim, Wu-Kang; Park, Jun-Young; Lee, Seung-Wook; Kim, Seong-Yeon; Yu, Ji-Man; et al, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.19, pp.52 - 55, 2020-01 |
| A Vertically Integrated Junctionless Nanowire Transistor Lee, Byung-Hyun; Hur, Jae; Kang, Min-Ho; Bang, Tewook; Ahn, Dae-Chul; Lee, Dongil; Kim, Kwang-Hee; et al, NANO LETTERS, v.16, no.3, pp.1840 - 1847, 2016-03 |
| Abnormal electrical characteristics of multi-layered MoS2 FETs attributed to bulk traps Kim, Choong-Ki; Yu, Chan Hak; Hur, Jae; Bae, Hagyoul; Jeon, Seung-Bae; Park, Hamin; Kim, Yong Min; et al, 2D MATERIALS, v.3, no.1, pp.015007, 2016-03 |
| All-Solid-State Ion Synaptic Transistor for Wafer-Scale Integration with Electrolyte of a Nanoscale Thickness Yu, Ji-Man; Lee, Chungryeol; Kim, Da-Jin; Park, Hongkeun; Han, Joon-Kyu; Hur, Jae; Kim, Jin-Ki; et al, ADVANCED FUNCTIONAL MATERIALS, v.31, no.23, pp.2010971, 2021-06 |
| An Optimum Strategy for the Low Voltage Operation of the Mechanical Switch Lee, Byung-Hyun; Kang, Min-Ho; Hur, Jae; Ahn, Dae-Chul; Lee, Dong-Il; Bae, Hagyoul; Choi, Yang-Kyu, IEEE NANO 2015, IEEE, 2015-07-29 |
| Compact model for multiple-gate junctionless FETs = 다중 게이트 정션리스 트랜지스터의 컴팩트 모델링link Hur, Jae; 허재; et al, 한국과학기술원, 2015 |
| Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode Hur, Jae; Lee, Byung-Hyun; Kang, Min-Ho; Ahn, Dae-Chul; Bang, Tewook; Jeon, Seung-Bae; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.37, no.5, pp.541 - 544, 2016-05 |
| Cryogenic Storage Memory with High-Speed, Low-Power, and Long-Retention Performance Hur, Jae; Kang, Dongsuk; Moon, Dong-Il; Yu, Jiman; Choi, Yang-Kyu; Shimeng, Yu, ADVANCED ELECTRONIC MATERIALS, v.9, no.6, 2023-06 |
| Demonstration of a Curable Nanowire FinFET Using Punchthrough Current to Repair Hot-Carrier Damage Park, Jun-Young; Hur, Jae; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.39, no.2, pp.180 - 183, 2018-02 |
| Demonstration of Thermally-Assisted Programming with High Speed and Improved Reliability for Junctionless Nanowire NOR Flash Memory Yu, Ji-Man; Park, Jun-Young; Lee, Geon-Beom; Han, Joon-Kyu; Kim, Myung-Su; Hur, Jae; Yun, Dae-Hwan; et al, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.18, pp.1110 - 1113, 2019-10 |
| Effect of Off-state Stress on Gate-Induced Drain Leakage by Interface Traps in Buried-Gate FETs Lee, Geon-Beom; Kim, Choong-Ki; Yoo, Min-Soo; Hur, Jae; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.66, no.12, pp.5126 - 5132, 2019-11 |
| Effects of Post Metal and Forming Gas Annealing on Characteristics of Ferroelectric FinFETs with HfZrOX Gate Dielectric Seo, Myung Soo; Kang, Min Ho; Kim, Wu Kang; Hur, Jae; Yun, Seok Jung; Kim, Hoon; Hong, Seung Bum; et al, 2018 MRS Fall Meeting & Exhibit, 2018 MRS Fall Meeting, 2018-11-28 |
| First Demonstration of a Logic-process Compatible Junctionless Ferroelectric FinFET Synapse for Neuromorphic Applications Seo, Myungsoo; Kang, Min Ho; Jeon, Seung-Bae; Bae, Hagyoul; Hur, Jae; Jang, Byung Chul; Yun, Seokjung; et al, IEEE ELECTRON DEVICE LETTERS, v.39, no.9, pp.1445 - 1448, 2018-09 |
| Gateless and Capacitorless Germanium Biristor with a Vertical Pillar Structure Bae, Hagyoul; Lee, Geon Beom; Hur, Jae; Park, Jun Young; Kim, Da Jin; Kim, Myung Su; Choi, Yang-Kyu, MICROMACHINES, v.12, no.8, 2021-07 |
| Highly Biased Linear Condition Method for Separately Extracting Source and Drain Resistance in MOSFETs Kim, Gun-Hee; Bae, Hagyoul; Hur, Jae; Kim, Choong-Ki; Lee, Geon-Beom; Bang, Tewook; Son, Yoon-Ik; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.2, pp.419 - 423, 2018-02 |
| Impact of crystalline damage on a vertically integrated junctionless nanowire transistor Ahn, Dae-Chul; Lee, Byung-Hyun; Kang, Min-Ho; Hur, Jae; Bang, Tewook; Choi, Yang-Kyu, APPLIED PHYSICS LETTERS, v.109, no.18, 2016-10 |
| Improved Split C-V Technique for Accurate Extraction of Mobility by Considering Effective Inversion Charges in p-Channel Si0.8Ge0.2 MOSFET Bang, Te-Wook; Bae, Hagyoul; Kim, Choong-Ki; Hur, Jae; Park, Jun-Young; Ahn, Dae-Chul; Kim, Gun-Hee; et al, 한국 반도체 학술 대회, 한국 반도체 학술 대회, 2016-02-23 |
| Improved Technique for Extraction of Effective Mobility by Considering Gate Bias-Dependent Inversion Charges in a Floating-Body Si/SiGe pMOSFET Bae, Hagyoul; Bang, Tewook; Kim, Choong-Ki; Hur, Jae; Kim, Seyeob; Jeon, Chang-Hoon; Park, Jun-Young; et al, JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.17, no.5, pp.3247 - 3250, 2017-05 |
| Investigation of Low-Frequency Noise in Nonvolatile Memory Composed of a Gate-All-Around Junctionless Nanowire FET Jeong, Ui-Sik; Kim, Choong-Ki; Bae, Hagyoul; Moon, Dong-Il; Bang, Tewook; Choi, Ji-Min; Hur, Jae; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.63, no.5, pp.2210 - 2213, 2016-05 |
| Joule Heating to Enhance the Performance of a Gate-All-Around Silicon Nanowire Transistor Jeon, Chang-Hoon; Park, Jun-Young; Seol, Myeong-Lok; Moon, Dong-Il; Hur, Jae; Bae, Hagyoul; Jeon, Seung-Bae; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.63, no.6, pp.2288 - 2292, 2016-06 |
| Low-Frequency Noise in Hysteresis-Free Multilayer MoS2 FETs Yu, Chan Hak; Kim, Choong Ki; Hur, Jae; Choi, Yang-Kyu; Choi, Sung-Yool, ICEIC 2015, ICEIC 2015(International Conference on Electronics, Information and Communication), 2015-01-28 |
| Nature-Replicated Nano-in-Micro Structures for Triboelectric Energy Harvesting Seol, Myeong-Lok; Woo, Jong-Ho; Lee, Dong-Il; Im, Hwon; Hur, Jae; Choi, Yang-Kyu, SMALL, v.10, no.19, pp.3887 - 3894, 2014-10 |
| Off-state leakage in MOSFET considering source/drain extension regions Hur, Jae; Jeong, Woo Jin; Shin, Mincheol; Choi, Yang-Kyu, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.36, no.8, pp.085018, 2021-08 |
| Optimization of the intrinsic length of a PIN diode for a reconfigurable antenna Kim, Da-Jin; Bang, Tewook; Hur, Jae; Kim, Choong-Ki; Choi, Yang-Kyu; Kim, Cheol Ho; Park, Bonghyuk, 15th International Conference on Electronics, Information, and Communications, ICEIC 2016, Institute of Electrical and Electronics Engineers Inc., 2016-01 |
| Reconfigurable Yagi-Uda antenna based on a silicon reflector with a solid-state plasma Kim, Da-Jin; Park, Sangjun; Kim,Cheol Ho; Hur, Jae; Kim, Choong-Ki; Cho, Young-Kyun; Ko, Jun-Bong; et al, SCIENTIFIC REPORTS, v.7, 2017-12 |
| Reply to Comments by Ortiz-Conde et al. Kim, Gun-Hee; Bae, Hagyoul; Hur, Jae; Kim, Choong-Ki; Lee, Geon-Bum; Bang, Tewook; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.9, pp.4022 - 4024, 2018-09 |
| Scalable In-Memory Clustered Annealer with Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems Ku, Anni; Hur, Jae; Luo, Yuan-Chun; LI, Hai; Nikonov, Dmitri E.; Young, Ian; Choi, Yang-Kyu; et al, IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.13, no.1, pp.422 - 435, 2023-03 |
| Scalable in-memory clustered annealer with temporal noise of FinFET for the travelling salesman problem Lu, Anni; Choi, Yang-Kyu; Hur, Jae; Luo, Yuan-Chun; Li, Hai; Nikonov, Dmitri; Young, Ian; et al, 68th IEEE International Electron Devices Meeting, IEDM 2022, IEEE, 2022-12-03 |
| Schottky Tunneling Effects in a Tunnel FET Hur, Jae; Jeong, Woo Jin; Shin, Mincheol; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.12, pp.5223 - 5229, 2017-12 |
| Silicon-Based Yagi-Uda Antenna Reflector Hur, Jae; Kim, Choong-Ki; Kim, Da-Jin; Bang, Tae-Wook; Choi, Yang-Kyu; Cho, Young-Gyun; Kim Cheol-Ho; et al, ICEIC 2017, International Conference on Electronics, Information, and Communication (ICEIC), 2017-01-12 |
| Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor Lee, Dong-Il; Lee, Byung-Hyun; Yoon, Jinsu; Ahn, Dae-Chul; Park, Jun-Young; Hur, Jae; Kim, Myung-Su; et al, ACS NANO, v.10, no.12, pp.10894 - 10900, 2016-12 |
| Transistor leakage considering source/drain extension region = 소스/드레인 영역이 고려된 트랜지스터 누설전류 연구link Hur, Jae; Choi, Yang-Kyu; et al, 한국과학기술원, 2019 |
| Tunneling Effects in a Charge-Plasma Dopingless Transistor Hur, Jae; Moon, Dong-Il; Han, Jin-Woo; Kim, Gun-Hee; Jeon, Chang-Hoon; Choi, Yang-Kyu, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.16, no.2, pp.315 - 320, 2017-03 |
| Two-terminal biristor with polysilicon emitter layer and method of manufacturing the same Choi, Yang-Kyu; Son, Jun Woo; Hur, Jae |
| Ultra-Fast Erase Method of SONOS Flash Memory by Instantaneous Thermal Excitation Ahn, Dae-Chul; Seol, Myeong-Lok; Hur, Jae; Moon, Dong-Il; Lee, Byung-Hyun; Han, Jin-Woo; Park, Jun-Young; et al, IEEE ELECTRON DEVICE LETTERS, v.37, no.2, pp.190 - 192, 2016-02 |
| Vertically Integrated Multiple Nanowire Field Effect Transistor Lee, Byung Hyun; Kang, Min Ho; Ahn, Dae Chul; Park, Jun Young; Bang, Tewook; Jeon, Seung Bae; Hur, Jae; et al, NANO LETTERS, v.15, no.12, pp.8056 - 8061, 2015-12 |
| Vertically stacked thin triboelectric nanogenerator for wind energy harvesting Seol, Myeong-Lok; Woo, Jong-Ho; Jeon, Seung-Bae; Kim, Daewon; Park, Sang-Jae; Hur, Jae; Choi, Yang-Kyu, NANO ENERGY, v.14, pp.201 - 208, 2015-05 |
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