A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

Abstract

A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poisson's equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage (VT) equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of VT shows good agreement with the simulation results down to a channel length <20 nm. The variability of VT is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated.