Effect of Off-state Stress on Gate-Induced Drain Leakage by Interface Traps in Buried-Gate FETs

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The gate-induced drain leakage (GIDL) current is one of the major leakage sources in a dynamic random-access memory (DRAM) cell transistor. In addition to band-to-band tunneling (BTBT), which causes GIDL in the gate-to-drain overlap region, the generation of interface traps in the gate dielectric increases the GIDL current by trap-assisted two-step tunneling (TATT). In this article, the influence of OFF-state stress on the generation of the interface traps, which deteriorates GIDL, was quantitatively analyzed with charge pumping (CP) characterization method in buried-channel array transistors (BCATs) for DRAM cells. The applied stress increased the GIDL current while simultaneously degrading device performance including such as transconductance ( $\text{g}_{\text {m}}$ ) and ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ), due to the generation of the interface traps. By using the CP characterization, the interface traps were spatially profiled along the gate-to-drain overlap region in the junction. Trap distribution inside the energy bandgap was also characterized.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-11
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.66, no.12, pp.5126 - 5132

ISSN
0018-9383
DOI
10.1109/TED.2019.2947603
URI
http://hdl.handle.net/10203/268879
Appears in Collection
EE-Journal Papers(저널논문)
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