A Study of High-Temperature Effects on an Asymmetrically Doped Vertical Pillar-Type Field-Effect Transistor

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The effects of high temperature on an asymmetrically doped vertical pillar-type metal-oxide-semiconductor field-effect transistor (MOSFET) were investigated. An asymmetrically doped source and drain (SD) can be easily formed in a vertical pillar-type FET due to the unique pillar structure. When high temperature is applied to the asymmetric SD of a vertical pillar-typed silicon nanowire, it affects mobility and carrier injection differently. It decreases mobility by phonon scattering for heavily doped S and intermediately doped D. In contrast, it enhances carrier injection for intermediately doped S and heavily doped D. Thus the ON-state current (I-ON) shows opposite dependencies at high temperature. This tendency was verified by electrical measurements and supporting simulations.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2020-01
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.19, pp.52 - 55

ISSN
1536-125X
DOI
10.1109/TNANO.2019.2958099
URI
http://hdl.handle.net/10203/271661
Appears in Collection
EE-Journal Papers(저널논문)
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