Schottky Tunneling Effects in a Tunnel FET

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Tunnel FETs (TFETs) have attracted a great deal of attention due to their steep subthreshold swing (SS) of less than 60 mV/dec, which overcomes the theoretical constraint imposed by the thermal limit in a conventional inversion-mode (IM) FET. Based on its advantages as a short-channel device with low stand-by power consumption, TFETs shows promise to replace IM-FETs. As the channel length is shortened to minimize the total gate pitch; however, the gate sidewall spacer is miniaturized as well. In this paper, the influence of junction extension length (L-ext) on TFET behavior is discussed where the length of the gate spacer is assumed to be the gap between the source and drain (S/D) electrodes and the gate edge. It was found that, when L-ext is aggressively scaled down, having S/D electrodes (silicide or metal) with identical work functions (WFs) leads to a severely high OFF-current (I-OFF) and high SS. By adopting separate asymmetric WFs for the p-type and n-type S/D electrodes, the on/off characteristics were improved with suppressed IOFF and steeper slopes. Itwas also shownthat thedeviceperformanceof a TFET with higher source-side doping concentrations (similar to 5 x10(20) cm(-3)) can be further improved even at the aggressively scaled-down L-ext by boosting the on-current.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-12
Language
English
Article Type
Article
Keywords

FIELD-EFFECT TRANSISTORS; DESIGN; ANNEAL; TFETS; NM

Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.12, pp.5223 - 5229

ISSN
0018-9383
DOI
10.1109/TED.2017.2757260
URI
http://hdl.handle.net/10203/228430
Appears in Collection
EE-Journal Papers(저널논문)
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