Browse by Subject MOSFET
Showing results 48 to 81 of 81
| Modeling and simulation study on the nano-scaled schottky-barrier junction and MOSFETs = 나노 수준의 크기를 갖는 쇼트키 배리어 접합 구조와 모스펫에 대한 모델링 및 시뮬레이션 연구link Lee, Jaehyun; 이재현; et al, 한국과학기술원, 2016 |
| Moores law lives on - Ultra-thin body SOI and FinFET CMOS transistors look to continue Moores law for many years to come Chang, LL; Choi, Yang-Kyu; Kedzierski, J; Lindert, N; Xuan, PQ; Bokor, J; Hu, CM; et al, IEEE CIRCUITS DEVICES, v.19, no.1, pp.35 - 42, 2003-01 |
| MOSFET을 이용한 우리별 1호에서의 total dose effect 연구 = Study of the total dose effect measured on KITSAT-1 using the MOSFET detectorlink 이대희; Lee, Dae-Hee; et al, 한국과학기술원, 1997 |
| Nanoscale CMOS spacer FinFET for the terabit era Choi, Yang-Kyu; King, TJ; Hu, CM, IEEE ELECTRON DEVICE LETTERS, v.23, no.1, pp.25 - 27, 2002-01 |
| Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu, APPLIED PHYSICS LETTERS, v.100, no.9, 2012-02 |
| Performance Assessment of III-V Channel Ultra-Thin-Body Schottky-Barrier MOSFETs Lee, Jaehyun; Shin, Mincheol, IEEE ELECTRON DEVICE LETTERS, v.35, no.7, pp.726 - 728, 2014-07 |
| Quantum simulation of device characteristics of silicon nanowire FETs Shin, Mincheol, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.6, no.2, pp.230 - 237, 2007-03 |
| Quantum simulation of nano-scale MOSFETs in the ballistic transport region = 나노 MOSFET 에서의 전자의 탄도전소에 대한 양자 시뮬레이션link Choi, Hyun-Hwan; 최현환; et al, 한국정보통신대학교, 2005 |
| Quantum transport of holes in 1D, 2D, and 3D devices: the k center dot p method Shin, Mincheol, JOURNAL OF COMPUTATIONAL ELECTRONICS, v.10, no.1-2, pp.44 - 50, 2011-06 |
| RF noise modeling of MOSFETslink Choi, Jeong-Ki; 최정기; et al, 한국정보통신대학원대학교, 2000 |
| Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced From Hot-Carrier Injection Park, Jun-Young; Moon, Dong-Il; Seol, Myeong-Lok; Kim, Choong-Ki; Jeon, Chang-Hoon; Bae, Hagyoul; Bang, Tewook; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.63, no.3, pp.910 - 915, 2016-03 |
| Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors Choi, Sung-Jin; Moon, Dong-Il; Kim, Sung-Ho; Duarte, Juan P.; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.32, no.2, pp.125 - 127, 2011-02 |
| Significance of gate oxide thinning below 1.5 nm on 1/f noise behavior in n-channel metal-oxide-semiconductor field-effect transistors under electrical stress Mheen, B; Kim, M; Song, YJ; Hong, Songcheol, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, v.45, no.6A, pp.4943 - 4947, 2006-06 |
| Silicidation of Mo-alloyed ytterbium: Mo alloying effects on microstructure evolution and contact properties Na, Sekwon; Kang, Jun-gu; Choi, Juyun; Lee, Nam-Suk; Park, Chan Gyung; Kim, Hyoungsub; Lee, Seok-Hee; et al, ACTA MATERIALIA, v.92, pp.1 - 7, 2015-06 |
| Simulation and ground test for the total ionizing dose effects of STSAT-2 Ryu, Kwangsun; Shin, Goo-Hwan; Kim, Hyung-Myung; Kim, Sungjoon; Ko, Dai-Ho; Kim, Heejun; Min, KyoungWook, JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.50, no.5, pp.1552 - 1556, 2007-05 |
| Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era Choi, Yang-Kyu; King, TJ; Hu, CM, SOLID-STATE ELECTRONICS, v.46, no.10, pp.1595 - 1601, 2002-10 |
| Spin torque nano-oscillators directly integrated on a MOSFET Kang, Doo Hyung; Lee, Jaehyun; Jeong, Woo Jin; Shin, Mincheol, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.17, no.1, pp.122 - 127, 2018-01 |
| Sub-50 nm p-channel FinFET Huang, XJ; Lee, WC; Kuo, C; Hisamoto, D; Chang, LL; Kedzierski, J; Anderson, E; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.48, no.5, pp.880 - 886, 2001-05 |
| Sub-60-nm quasi-planar FinFETs fabricated using a simplified process Lindert, N; Chang, LL; Choi, Yang-Kyu; Anderson, EH; Lee, WC; King, TJ; Bokor, J; et al, IEEE ELECTRON DEVICE LETTERS, v.22, no.10, pp.487 - 489, 2001-10 |
| Surface-Roughness-Limited Mean Free Path in Silicon Nanowire Field Effect Transistors Jung, Hyo-Eun; Shin, Mincheol, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.60, no.6, pp.1861 - 1866, 2013-06 |
| Systematic characterization for RF small-signal parameter extraction of 28 nm FDSOI MOSFETs up to 110 GHz Yang, Xuejing; Lee, Seungkyeong; Hong, Songcheol; Yang, Kyoung-Hoon, MICROELECTRONICS JOURNAL, v.138, 2023-08 |
| Tensile-strained germanium CMOS integration on silicon Zang, H; Loh, WY; Ye, JD; Lo, GQ; Cho, Byung Jin, IEEE ELECTRON DEVICE LETTERS, v.28, no.12, pp.1117 - 1119, 2007-12 |
| The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances Kim, Jeong-Kyu; Kim, Gwang-Sik; Nam, Hyohyun; Shin, Changhwan; Park, Jin-Hong; Kim, Jong-Kook; Cho, Byung-Jin; et al, IEEE ELECTRON DEVICE LETTERS, v.35, no.12, pp.1185 - 1187, 2014-12 |
| Theoretical study of the surface roughness scattering effects on silicon nanowire FETs = 실리콘 나노와이어 트랜지스터에서의 표면 거칠기 충돌영향에 대한 이론연구link Jung, Hyo-Eun; 정효은; et al, 한국과학기술원, 2013 |
| Threshold Voltage Tuning Technique in Gate-All-Around MOSFETs by Utilizing Gate Electrode With Potential Distribution Park, Jun-Young; Bae, Hagyoul; Moon, Dong-Il; Jeon, Chang-Hoon; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.37, no.11, pp.1391 - 1394, 2016-11 |
| Transient charge trapping and detrapping properties of a thick SiO2/Al2O3 stack studied by short single pulse I-d-V-g Chang, Man; Jo, Minseok; Jung, Seungjae; Lee, Joonmyoung; Jeon, Sanghun; Hwang, Hyunsang, APPLIED PHYSICS LETTERS, v.94, no.26, 2009-06 |
| Triboelectric nanogenerator for a repairable transistor with self-powered electro-thermal annealing Kim, Weon-Guk; Han, Joon-Kyu; Tcho, Il-Woong; Park, Jun-Young; Yu, Ji-Man; Choi, Yang-Kyu, NANO ENERGY, v.76, pp.105000, 2020-10 |
| Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using Y Doped ZrO2 With Record-Low Leakage Current Lee, Tae In; Ahn, Hyunjun; 김민주; Shin, Eui Joong; Lee, Seung Hwan; Shin, Sung Won; Hwang, Wan Sik; et al, IEEE ELECTRON DEVICE LETTERS, v.40, no.4, pp.502 - 505, 2019-04 |
| Ultrathin-body SOI MOSFET for deep-sub-tenth micron era Choi, Yang-Kyu; Asano, K; Lindert, N; Subramanian, V; King, TJ; Bokor, J; Hu, CM, IEEE ELECTRON DEVICE LETTERS, v.21, no.5, pp.254 - 255, 2000-05 |
| Vacuum gate dielectric gate-all-around nanowire for hot carrier injection and bias temperature instability free transistor Han, Jin-Woo; Moon, Dong-Il; Oh, Jae Sub; Choi, Yang-Kyu; Meyyappan, M., APPLIED PHYSICS LETTERS, v.104, no.25, 2014-06 |
Vertical-tunneling field-effect transistor based on MoTe2/MoS2 2D-2D heterojunction Koo, Bondae; Shin, Gwang Hyuk; Park, Hamin; Kim, Hojin; Choi, Sung-Yool, JOURNAL OF PHYSICS D-APPLIED PHYSICS, v.51, no.47, pp.475101, 2018-10 |
| Vertically Integrated Unidirectional Biristor Moon, Dong-Il; Choi, Sung-Jin; Kim, Sung-Ho; Oh, Jae-Sub; Kim, Young-Su; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.32, no.11, pp.1483 - 1485, 2011-11 |
| 기판접착을 이용한 몸체접지형SOI nMOSFET에 대한 연구 = Study on grounded body SOI n-channel MOSFET by wafer bondinglink 강원구; Kang, Won-Gu; et al, 한국과학기술원, 1996 |
| 원자층증착법에 의한 $HfO_2$ 게이트절연막의 성장과 플라즈마처리에 의한 질화에 관한 연구 = Study on $HfO_2$ gate dielectric grown by atomic layer deposition and its nitridation by plasma treatmentlink 박건식; Park, Kun-Sik; et al, 한국과학기술원, 2011 |
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- 31,005 2020 - 2024
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