Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

Cited 252 time in webofscience Cited 0 time in scopus
  • Hit : 394
  • Download : 113
We experimentally investigate the sensitivity of threshold voltage (V(T)) to the variation of silicon nanowire (SiNW) width (W(si)) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the V(T) fluctuation caused by the W(si) variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the V(T) fluctuation related to the W(si) variation should be considered in junctionless transistors.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2011-02
Language
English
Article Type
Article
Keywords

DOUBLE-GATE; DEVICES; FINFET; MOSFET; NM

Citation

IEEE ELECTRON DEVICE LETTERS, v.32, no.2, pp.125 - 127

ISSN
0741-3106
DOI
10.1109/LED.2010.2093506
URI
http://hdl.handle.net/10203/100863
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 252 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0