Theoretical study of the surface roughness scattering effects on silicon nanowire FETs

Abstract

In recent years, the bulk Si MOSFETs have reached the nanometric scale, leading to an increased density integration on chip, but also to a strong gate control in order to reduce the short-channel- effects (SCEs). In particular, using new materials instead of silicon or developing various device structures have been achieved for high performances in scaled devices. For this reason, the nanowire-based MOSFETs with the multi-gate type have become the most interesting candidates to replace actual planar MOSFET devices, expected to reduce SCEs. Especially, gate-all-around (GAA) structure has outstanding immunity to SCEs showing the best electrostatic control in the inversion layer which contributes to the transport property.

One of the most important factor in considering transport properties in nanowire can be the surface roughness at the device/insulator interface and the easiest way to assess sub-10 nm device performance is the simulation work. Hence, we have computationally realized the surface roughness at the interfaces of the silicon nanowire transistors according to the autocorrelation function assuring that the surface roughness can be a significant scattering mechanism.

In this thesis, we use a full quantum treatment to investigate the surface roughness-related physics and device transport characteristics by employing the non-equilibrium Green`s function (NEGF) approach. The overall characteristics of the low-field mobility and mean free path (MFP) are calculated with respect to the channel length (L), wire width (W), and the root-mean-square (RMS) of the surface roughness. Large amount of the mobility reduction for particularly small nanowire is observed, implying that the electrons near the rough interface experience more scattering as size is becoming smaller. And the behavior of the MFP with respect to the SR is investigated by the single parameter, RMS/W, showing that the MFP...