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Showing results 1 to 13 of 13

1
A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

Chung, D.; Ryu, C.; Kim, H.; Lee, C.; Kim, J.; Kim, J.; Bae, K.; et al, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.514 - 614, 2005-02-06

2
A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design

Lee, W.; Ryu, C.; Cho, J.; Song, E.; Kim, Joungho, 2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010, pp.334 - 337, APEMC 2010, 2010-04-12

3
A frequency tunable resonant clock distribution scheme using bond-wire inductor

Lee, W.; Pak, J.S.; Pak, J.; Ryu, C.; Park, J.; Kim, Joungho, 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008, pp.24 - 26, IEEE, 2008-12-10

4
Analysis of the effect of AC noise on DC bias of VGA for UHF RFID using chip-package co-modeling and simulation

Lee, H.; Shim, Y.; Park, H.; Ryu, C.; Yoon, C.; Kim, Joungho, 9th Electronics Packaging Technology Conference, EPTC 2007, pp.591 - 594, IEEE, 2007-12-12

5
Analysis of the effect of digital power ground noise on active balun in UHF RTID SiP

Park, J.; Ryu, C.; Yoon, C.; Koo, K.; Kim, Joungho, 9th Electronics Packaging Technology Conference, EPTC 2007, pp.586 - 590, IEEE, 2007-12-12

6
Effect of EBG structures for reducing noise in multi-layer PCBs for digital systems

Chung, D.; Kim, T.H.; Ryu, C.; Engin, E.; Swaminathan, M.; Kim, Joungho, IEEE 15th Topical Meeting on Electrical Performance of Electronic Packaging, pp.253 - 256, IEEE, 2006-10-23

7
Electrical characterization of Trough Silicon Via (TSV) depending on structural and material parameters based on 3D full wave simulation

Pak, J.S.; Ryu, C.; Kim, Joungho, International Conference on Electronic Materials and Packaging, EMAP 2007, IEEE, 2007-11-19

8
Estimation of data-dependent jitter using single pulse analysis method in high-speed differential signaling

Song, E.; Lee, J.; Kim, J.; Kam, D.G.; Ryu, C.; Kim, Joungho, ESTC 2006 - 1st Electronics Systemintegration Technology Conference, pp.741 - 746, IEEE, 2006-09-05

9
High frequency electrical circuit model of chip-to-chip vertical via iterconnection for 3-D chip stacking package

Ryu, C.; Chung, D.; Lee, J.; Lee, K.; Oh, T.; Kim, Joungho, 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005, v.2005, pp.151 - 154, 2005-10-24

10
High frequency electrical model of through wafer via for 3-D stacked chip packaging

Ryu, C.; Lee, J.; Lee, H.; Lee, K.; Oh, T.; Kim, Joungho, ESTC 2006 - 1st Electronics Systemintegration Technology Conference, pp.215 - 220, IEEE, 2006-09-05

11
Implementation of low jitter clock distribution using chip-package hybrid interconnection

Ryu, C.; Chung, D.; Bae, K.; Yu, J.; Kim, Joungho, IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp.291 - 294, IEEE, 2004-10-25

12
Jitter suppressed on-chip clock distribution using package plane cavity resonance

Lee, W.; Ryu, C.; Park, J.; Kim, Joungho, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.427 - 430, IEEE, 2008-05-19

13
Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

Pak, J.S.; Ryu, C.; Kim, J.; Shim, Y.; Kim, G.; Kim, Joungho, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.351 - 354, IEEE, 2008-05-19

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