A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design

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Publisher
APEMC 2010
Issue Date
2010-04-12
Language
ENG
Citation

2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010, pp.334 - 337

URI
http://hdl.handle.net/10203/164029
Appears in Collection
EE-Conference Papers(학술회의논문)
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