High frequency electrical model of through wafer via for 3-D stacked chip packaging

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Publisher
IEEE
Issue Date
2006-09-05
Language
ENG
Citation

ESTC 2006 - 1st Electronics Systemintegration Technology Conference, pp.215 - 220

URI
http://hdl.handle.net/10203/18703
Appears in Collection
EE-Conference Papers(학술회의논문)
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