Browse "School of Electrical Engineering(전기및전자공학부)" by Subject NM

Showing results 1 to 12 of 12

1
A spacer patterning technology for nanoscale CMOS

Choi, Yang-Kyuresearcher; King, TJ; Hu, CM, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.49, no.3, pp.436 - 441, 2002-03

2
A Vertically Integrated Junctionless Nanowire Transistor

Lee, Byung-Hyun; Hur, Jae; Kang, Min-Ho; Bang, Tewook; Ahn, Dae-Chul; Lee, Dongil; Kim, Kwang-Hee; et al, NANO LETTERS, v.16, no.3, pp.1840 - 1847, 2016-03

3
An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs

Huh, In; Park, Sangchun; Shin, Mincheolresearcher; Choi, Woo Young, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.8, pp.3502 - 3507, 2017-08

4
Doping-Free Nanoscale Complementary Carbon-Nanotube Field-Effect Transistors with DNA-Templated Molecular Lithography

Kim, KH; Kim, JH; Huang, XJ; Yoo, SM; Lee, SangYupresearcher; Choi, Yang-Kyuresearcher, SMALL, v.4, no.11, pp.1959 - 1963, 2008-11

5
High-k HfxZr1-xO2 Ferroelectric Insulator by Utilizing High Pressure Anneal

Das, Dipjyoti; Jeon, Sanghunresearcher, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.67, no.6, pp.2489 - 2494, 2020-06

6
Schottky Tunneling Effects in a Tunnel FET

Hur, Jae; Jeong, Woo Jin; Shin, Mincheolresearcher; Choi, Yang-Kyuresearcher, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.12, pp.5223 - 5229, 2017-12

7
Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

Choi, Sung-Jin; Moon, Dong-Il; Kim, Sung-Ho; Duarte, Juan P.; Choi, Yang-Kyuresearcher, IEEE ELECTRON DEVICE LETTERS, v.32, no.2, pp.125 - 127, 2011-02

8
Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era

Choi, Yang-Kyuresearcher; King, TJ; Hu, CM, SOLID-STATE ELECTRONICS, v.46, no.10, pp.1595 - 1601, 2002-10

9
Surface plasmon-assisted nano-lithography with a perfect contact aluminum mask of a hexagonal dot array

Kim, Eun Sung; Kim, Yong Min; Choi, Kyung Cheolresearcher, PLASMONICS, v.11, no.5, pp.1337 - 1342, 2016-10

10
The Effect of the Ratio of Lines to Spaces for Nanolithography Using Surface Plasmons

Kim, Eun Sung; Choi, Kyung Cheolresearcher, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.13, no.2, pp.203 - 207, 2014-03

11
Vertically Integrated Multiple Nanowire Field Effect Transistor

Lee, Byung Hyun; Kang, Min Ho; Ahn, Dae Chul; Park, Jun Young; Bang, Tewook; Jeon, Seung Bae; Hur, Jae; et al, NANO LETTERS, v.15, no.12, pp.8056 - 8061, 2015-12

12
Vertically Integrated Nanowire-Based Unified Memory

Lee, Byung-Hyun; Ahn, Dae-Chul; Kang, Min-Ho; Jeon, Seung-Bae; Choi, Yang-Kyuresearcher, NANO LETTERS, v.16, no.9, pp.5909 - 5916, 2016-09

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