Browse "EE-Conference Papers(학술회의논문)" by Author Ryu, Seung-Tak
Showing results 1 to 52 of 52
| 1-bit and multi-bit envelope delta-sigma modulators for CDMA polar transmitters K., Woo-Young; Ki-Young K.; Ryu, Seung-Tak; Jae-Kil J.; Park, Chul Soon, 2008 Asia Pacific Microwave Conference, APMC 2008, IEEE, 2008-12-16 |
| A 0.014mm2 9b switched-current DAC for AMOLED mobile display drivers Kim, H.-S.; Jeon, J.-Y.; Lee, S.-W.; Yang, J.-H.; Ryu, Seung-Tak; Cho, Gyu-Hyeong, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, pp.316 - 317, IEEE, 2011-02-20 |
| A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section Kim, Jong Pal; Lee, Wonseok; Suh, Junyeub; Lee, Hyungwoo; Lee, Kyuil; Ahn, Ho Young; Seo, Min-Jae; et al, 42nd Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC), pp.4012 - 4015, IEEE, 2020-07 |
| A 10b 50MS/s pipelined ADC with opamp current reuse Ryu, Seung-Tak; Song, Bang-Sup; Bacrania, Kanti, IEEE, pp.216 - 217, 2006-02 |
| A 10b linear interpolation DAC using body-transconductance control for AMLCD column driver Park, C.; Kim, K.-D.; Lee, S.-W.; Park, G.-S.; Ryu, Seung-Tak; Cho, G.-H., 2010 6th IEEE Asian Solid-State Circuits Conference, pp.165 - 168, IEEE, 2010-11-08 |
| A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration Park, Chang Un; Chung, Jaehyun; Ryu, Seung-Tak, 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, IEEE, 2023-04-26 |
| A 14b-linear capacitor self-trimming pipelined ADC Ryu, Seung-Tak; Ray, S.; Song, B.-S.; Cho, G.-H.; Bacrania, K., Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference, v.47, pp.464 - 0, 2003-02-15 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-um CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, International Symposium on Integrated Circuits and Systems, pp.3617 - 3627, IEEE CAS Society, 2018-09-02 |
| A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique Hong, Hyeok-Ki; Kang, HW; Jo, DS; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25 |
| A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS Sung, BRS; Jo, DS; Jang, IH; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25 |
| A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-order SARAssisted CT DSM with 1-0 MASH and DNC Lozada, Kent Edrian; Lee, Dong-Hun; Kim, Ye Dam; Kim, Ho-Jin; Cho, Youngjae; Choi, Michael; Ryu, Seung-Tak, 2023 IEEE Asian Solid-State Circuits Conference, IEEE, 2023-11-08 |
| A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC Jang, Il-Hoon; Seo, Min-Jae; Kim, Mi-Young; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sun-Woo; Choi, Michael; et al, Symposium on VLSI Circuits, pp.C34 - C35, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-06 |
| A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting Im, Jong-Pil; Wang, Se-Won; Lee, Kang-Ho; Woo, Young-Jin; Yuk, Young-Sub; Kong, Tae-Hwang; Hong, Sung-Wan; et al, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, pp.104 - 106, IEEE, 2012-02-20 |
| A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC Seo, Min-Jae; Kim, Ye Dam; Chung, Jae-Hyun; Ryu, Seung-Tak, 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C72 - C73, IEEE, 2019-06-11 |
| A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling Lozada, Kent Edrian; Ryu, Seung-Tak, 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022, IEEE, 2022-08-10 |
| A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization Kim, Ye-Dam; Chung, Jae-Hyun; Lozada, Kent Edrian; Chang, Dong-Jin; Ryu, Seung-Tak, 17th IEEE Asian Solid-State Circuits Conference (A-SSCC) - Integrated Circuits and Systems for the Connection of Intelligent Things, IEEE, 2021-11-07 |
| A 5.6mV Inter-Channel DVO 10b Column-Driver IC with Mismatch-Free Switched-Capacitor Interpolation for Mobile Active-Matrix LCDs Kim, Hyun-Sik; Yang, Jun-Hyeok; Park, Sang-Hui; Ryu, Seung-Tak; Cho, Gyu-Hyeong, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013, pp.392 - 393, IEEE, 2013-02-20 |
| A 54-μW fast-settling arterial pulse wave sensor for wrist watch type system Kim, Kwantae; Kim, Minseo; Cho, Hyunwoo; Lee, Kwonjoon; Ryu, Seung-Tak; Yoo, Hoi-Jun, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, pp.1082 - 1085, Institute of Electrical and Electronics Engineers Inc., 2016-05 |
| A 550μW 10b 40MS/s SAR ADC with multistep addition-only digital error correction Cho, S.-H.; Lee, C.-K.; Kwon, J.-K.; Ryu, Seung-Tak, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, pp.561 - 564, IEEE, 2010-09-19 |
| A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration Sung, BRS; Lee, CK; Kim, W; Kim, JI; Hong, HK; Oh, GG; Lee, CH; et al, 2013 IEEE Asian Solid-State Circuits Conference, pp.281 - 284, IEEE, 2013-11-13 |
| A 6-bit 10-GS/s 63-mW 4x TI Time-Domain Interpolating Flash ADC in 65-nm CMOS Oh, DR; Kim, JI; Seo, MJ; Kim, JG; Ryu, Seung-Tak, European Solid-State Circuits Conference, IEEE, 2015-09-17 |
| A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration Kim, WooCheol; Jo, Dong Shin; Roh, Yi-Ju; Kim, Ye Dam; Ryu, Seung-Tak, 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C138 - C139, IEEE, 2019-06-11 |
| A 6bit 1GS/s Time-interleaved Flash-SAR A/D Converter for Ultra Wide Band System Ryu, Seung-Tak; Sung, B.R.S.; Lee, Chang-Kyo; Kim, Jong-In, TriSAI 2010, 2010 |
| A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control Hong, Hyeok-Ki; Kim, Wan; Park, Sun-Jae; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, 2012 IEEE Custom Integrated Circuits Conference, IEEE, 2012-09-10 |
| A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS Moon, Kyoung-Jun; Kang, Hyun-Wook; Jo, Dong-Shin; Kim, Mi-Young; Baek, Seung-Yeob; Choi, Michael; Ko, Hyung-Jong; et al, 31st Symposium on VLSI Circuits, pp.C94 - C95, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-07 |
| A CMOS linear preamplifier design for electret microphones Park, G.-S.; Ryu, Seung-Tak, 2008 International SoC Design Conference, ISOCC 2008, v.2, IEEE, 2008-11-24 |
| A CMOS programmable gain amplifier with constant current-density based transconductance control Kang, S.Y.; Ryu, Seung-Tak; Park, Chul Soon, 2010 32nd IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2010, pp.37 - 140, IEEE, 2010-10-03 |
| A Direct Down Converted Low-Jitter Band Pass Delta Sigma Receiver with Frequency Translating Technique and Sinusoidal RF DAC So Young Kang; Dongmin Kang; Hi Yuen Song; Hyunseok Choi; Oh, Inn Yeal; Ryu, Seung-Tak; Park, Chul Soon, 2012 Asia-Pacific Microwave Conference, APMC, 2012-12-04 |
| A Dual Channel 10-b Pipelined ADC for Intelligent Transport System Ryu, Seung-Tak; Oh, Ghil-Geun, International Conference on Electron Devices and Solid-State Circuits, IEEE Electron Devices Society, 2014-06-18 |
| A Fully Differential Rail-to-Rail Input Dynamic Latch Kim, Jong-In; Ryu, Seung-Tak, ITC-CSCC, pp.477 - 479, ITC-CSCC, 2009 |
| A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels Yang, Jun-Hyeok; Park, Sang-Hui; Choi, Jung-Min; Kim, Hyun-Sik; Park, Chang-Byung; Ryu, Seung-Tak; Cho, Gyu-Hyeong, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013, pp.390 - 391, IEEE, 2013-02-20 |
| A Low-Power Fast Readout Circuit Using a Dual-Mode Sensing Algorithm for Medium-Sized Capacitive Touch-Screen Panels Kim, Hyeon-June; Jo, Dong-Shin; Yang,Jun-Hyeok; Ryu, Seung-Tak, SID International Symposium, SID (The Society of Information Display), 2014-06-04 |
| A novel readout IC with high noise immunity for charge-based touch screen panels Yang, J.H.; Jung, S.C.; Woo, Y.J.; Jeon, J.Y.; Lee, S.W.; Park, C.B.; Kim, H.S.; et al, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, pp.211 - 214, IEEE, 2010-09-19 |
| A Power Efficient Conversion Techique for SAR ADC Ryu, Seung-Tak; Cho, Sang-Hyun, TriSAI, pp.307 - 309, 2009 |
| A Reference-Driver Free ADC Architecture Ryu, Seung-Tak; Lee, Chang-Kyo; Cho, Sang-Hyun, TriSAI, pp.304 - 306, 2009 |
| A regulator-free 84dB DR audio-band ADC for compact digital microphones Le, H.-B.; Lee, S.-G.; Ryu, Seung-Tak, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp.365 - 368, IEEE, 2010-11-08 |
| A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs Chang, Dong Jin; Ryu, Seung-Tak, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, pp.174 - 175, Institute of Electrical and Electronics Engineers Inc., 2022-06 |
| A Resolution-Reconfigurable 12b-to-8b Successive-Approximation ADC for CMOS Image Sensor Hwang, SI; Kim, HJ; Ryu, Seung-Tak, Asian Image Sensors and Imaging Systems Symposium, IEEE SSCS Japan Chapter, 2014-12-02 |
| A sampling-based 128x128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel Kim, Hyun-Sik; Han, Sang-Wook; Yang, Jun-Hyeok; Kim, Sunil; Kim, Young; Kim, Sangwook; Yoon, Dae-Kun; et al, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, pp.110 - 112, IEEE, 2012-02-19 |
| A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye Dam; Kim, Jong-Pal; Chang, Dong-Jin; Lim, Won-Mook; Chung, Jaehyun; et al, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, pp.189 - 192, Institute of Electrical and Electronics Engineers Inc., 2019-11 |
| A time-domain latch interpolation technique for low power flash ADCs Kim, Join-In; Kim, Wan; Sung, Barosaim; Ryu, Seung-Tak, 2011 IEEE Custom Integrated Circuits Conference, IEEE, 2011-09-20 |
| A time-interleaved flash-SAR architecture for high speed A/D conversion Sung, B.R.S.; Cho, S.-H.; Lee, C.-K.; Kim, J.-I.; Ryu, Seung-Tak, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, pp.984 - 987, IEEE, 2009-05-24 |
| A Two-step 5b Logarithmic ADC with Minimum Step-size of 0.1% Full-scale for MLC Phase-Change Memory Readout Kwon, JW; Jin, DH; Kim, HJ; Hwang, SI; Shin, MC; Kang, JH; Ryu, Seung-Tak, Custom Integrated Circuits Conference(CICC), IEEE, 2014-09-17 |
| An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement Hong, Hyeok-Ki; Kang, Hyun-Wook; Sung, Barosaim; Lee, Choong-Hoon; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, 2013 IEEE International Solid-State Circuits Conference, IEEE, 2013-02-20 |
| An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd-Order Noise-Shaping Interpolating SAR ADC Chung, Jaehyun; Kim, Ye Dam; Park, Chang Un; Park, Kunwoo; Seo, Min-Jae; Ryu, Seung-Tak, 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, IEEE, 2023-04-25 |
| An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers Oh, Dong-Ryeol; Moon, Kyoung-jun; Lim, Won-mook; Kim, Yedam; An, Eun-ji; Ryu, Seung-Tak, Symposium on VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-10 |
| An Energy Pile-Up Resonance Circuit Extracting Maximum 422% Energy from Piezoelectric Material in a Dual-Source Energy-Harvesting Interface Yuk, Young Sub; Jung, Seung Chul; Gwon, Hui Dong; Choi, Sukhwan; Sung, Si Duk; Kong, Tae Hwang; Hong, SW; et al, 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014, pp.402 - 403, IEEE, 2014-02-10 |
| An incremental zoom sturdy MASH ADC Seo, Ki-Hoon; Jang, Il Hoon; Noh, Kyung-Joon; Ryu, Seung-Tak, Circuits and Systems (MWSCAS), 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-08-08 |
| An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation Lim, Seung-Yong; Mabilangan, Raymond; Chang, Dong-Jin; Cho, Young-Jae; Choi, Michael; Ryu, Seung-Tak, 17th IEEE Asian Solid-State Circuits Conference (A-SSCC) - Integrated Circuits and Systems for the Connection of Intelligent Things, IEEE, 2021-11-07 |
| CMOS Image Sensors with Delta Readout Scheme Kim, Hyeon-June; Hwang, Sun-Il; Chung, Jae-Hyun; Ryu, Seung-Tak, International SoC Design Conference, IEEE, 2017-11-07 |
| Delta Readout Scheme for Image-Dependent Power Savings in a CMOS Image Sensor with Multi-Column-Parallel SAR ADCs Kim, HJ; Hwang, SI; Kwon, JW; Jin, DH; Choi, BS; Lee, SG; Park, JH; et al, Asian Solid-State Circuits Conference, IEEE, 2015-11-10 |
| High-gain wide-bandwidth capacitor-less low-dropout regulator with zero insertion utilizing frequency response of inner loops Hong, Sung-Wan; Jung, Seungchul; Park, Changbyoung; Kong, Tae-Hwang; Jung, Min-Yong; Ryu, Seung-Tak; Cho, Gyu-Hyeong, 2013 IEEE Symposium on VLSI Circuits, SOVC 2013, pp.C168 - C169, IEEE, 2013-06-13 |
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