A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability

Abstract

This paper presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing owing to the capacitive level shifting bias scheme. In conjunction with 8x oversampling and the power-saving skip-reset technique that has the inherent chopping capability, the prototype 180nm CMOS 12b ADC operating at a 5.12 MS/s sampling rate achieved a 74.8 dB SNDR under a 1.5V supply voltage.