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Ryu, Seung-Tak (류승탁)
교수, School of Electrical Engineering(전기및전자공학부)

http://msicl.kaist.ac.kr

Research Area
Electronic Circuits, Integrated Circuits, Circuit Theory, Analog/Mixed-Signal Integrated Circuits
Co-researchers
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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision

    Roh, Yi-Ju; Chang, Dong-Jin; Ryu, Seung-Takresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.2833 - 2837, 2020-12

    2
    Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron

    창동진; Nam, Byeong-Gyu; Ryu, Seung-Takresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.12, pp.5189 - 5199, 2020-12

    3
    Recycling of Particulate Photoabsorbers for Highly Stable Solar Desalination Operation

    Kim, Kwanghyun; Kang, Jihun; Kim, Sun-, I; et al, ACS APPLIED ENERGY MATERIALS, v.3, no.9, pp.8295 - 8301, 2020-09

    4
    Air-Gap-Insensitive IPT Pad With Ferromagnetic and Conductive Plates

    Choi, Jin Soo; Jeong, Seog Y.; Choi, Byeung Guk; et al, IEEE TRANSACTIONS ON POWER ELECTRONICS, v.35, no.8, pp.7863 - 7872, 2020-08

    5
    New Curved Reflectors for Significantly Enhanced Solar Power Generation in Four Seasons

    Choi, Jin S.; Choi, Byeung G.; Kim, Ji H.; et al, ENERGIES, v.12, no.23, 2019-12

    6
    Three-dimensional solar steam generation device with additional non-photothermal evaporation

    Kim, Kwanghyun; Yu, Sunyoung; Kang, Se-Young; et al, DESALINATION, v.469, 2019-11

    7
    Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC

    Lee, Chang-Kyo; Ryu, Seung-Takresearcher, IET CIRCUITS DEVICES & SYSTEMS, v.13, no.8, pp.1277 - 1283, 2019-11

    8
    A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

    Moon, Kyoung-Jun; Jo, Dong-Shin; Kim, Wan; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2532 - 2542, 2019-09

    9
    A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers

    Jin, Dong-Hwan; Kwon, Ji-Wook; Seo, Min-Jae; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.6, pp.1812 - 1823, 2019-06

    10
    A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

    Oh, Dong-Ryeol; 김종인; Jo, Dong-Shin; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.1, pp.288 - 297, 2019-01

    11
    A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

    Seo, Min-Jae; Roh, Yi-Ju; Chang, Dong-Jin; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.12, pp.1904 - 1908, 2018-12

    12
    A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-mu m CMOS

    Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.11, pp.3617 - 3627, 2018-11

    13
    Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC)

    Lin, Tsung-Hsien; Yang, Chia-Hsiang; Ryu, Seung-Takresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.10, pp.2739 - 2740, 2018-10

    14
    A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme

    Kang, Hyun-Wook; Hong, Hyeok-Ki; Kim, Wan; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.9, pp.2584 - 2594, 2018-09

    15
    A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs

    Kim, Si-Nai; Kim, Woo Cheol; Seo, Min-Jae; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.9, pp.1154 - 1158, 2018-09

    16
    A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling

    Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1139 - 1148, 2018-04

    17
    A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration

    Chang, Dong-Jin; Seo, Min-Jae; Hong, Hyeok-Ki; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.3, pp.281 - 285, 2018-03

    18
    A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

    Hwang, Sun-Il; Chung, Jaehyun; Kim, Hyeon-June; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.3, pp.1119 - 1126, 2018-03

    19
    Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference

    Piessens, Tim; Ryu, Seung-Takresearcher; Hung, Chih-Ming; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.12, pp.3115 - 3118, 2017-12

    20
    A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

    Kim, Hyeon-June; Hwang, Sun-Il; Chung, Jaehyun; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.9, pp.2488 - 2497, 2017-09
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