An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers

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An 8b SAR-Flash ADC is proposed, where four reset-power-free complementary dynamic amplifiers (CDAs) are first engaged to a 4b loop-unrolled (LU) SAR conversion and then reutilized for a 4.5b fine interpolating-flash conversion. The hardware-reusing flash ADC not only saves power consumption and area but also reduces the number of conversion cycles. A prototype 1GS/s ADC in 28nm CMOS achieves 45.5dB SNDR at a Nyquist input with 2.55mW power consumption, leading to a FoMWalden of 16.6 fJ/c-s.
Publisher
Institute of Electrical and Electronics Engineers Inc.
Issue Date
2020-06-10
Language
English
Citation

Symposium on VLSI Circuits 2020

DOI
10.1109/VLSICircuits18222.2020.9163064
URI
http://hdl.handle.net/10203/277834
Appears in Collection
EE-Conference Papers(학술회의논문)
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