Browse "EE-Conference Papers(학술회의논문)" by Author Choi, Jaehyouk
Showing results 1 to 23 of 23
| 153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier Choi, Seojin; Yoo, Seyeon; Lee, Yongsun; Jo, Yongwoo; Lee, Jeonghyun; Lim, Younghyun; Choi, Jaehyouk, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, pp.185 - 186, Institute of Electrical and Electronics Engineers Inc., 2018-06-20 |
| 16.2 A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization Kim, Juyeop; Choi, Jaehyouk; Yoon, Heein; Lim, Younghyun; Lee, Yongsun; Cho, Yoonseo; Seong, Taeho, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019, pp.258 - 260, Institute of Electrical and Electronics Engineers Inc., 2019-02-19 |
| 30.9 A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019, pp.490 - 492, Institute of Electrical and Electronics Engineers Inc., 2019-02-19 |
| 32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk, 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp.442 - 444, IEEE, 2021-02-13 |
| 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique Kim, Juyeop; Jo, Yongwoo; Lim, Younghyun; Seong, Taeho; Park, Hangi; Yoo, Seyeon; Lee, Yongsun; et al, 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp.448 - 450, IEEE, 2021-02-13 |
| A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction Lee, Yongsun; Seong, Taeho; Lee, Jeonghyun; Hwanq, Chanwoong; Park, Hangi; Choi, Jaehyouk, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.266 - 268, Institute of Electrical and Electronics Engineers Inc., 2020-02-19 |
| A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk, 65th IEEE International Solid-State Circuits Conference, ISSCC 2018, pp.396 - 398, Institute of Electrical and Electronics Engineers Inc., 2018-02-13 |
| A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers Yoon, Heein; Kim, Juyeop; Park, Suneui; Lim, Younghyun; Lee, Yongsun; Bang, Jooeun; Lim, Kyoohyun; et al, 65th IEEE International Solid-State Circuits Conference, ISSCC 2018, pp.366 - 368, Institute of Electrical and Electronics Engineers Inc., 2018-02-13 |
| A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency Bang, Jooeun; Choi, Seojin; Yoo, Seyeon; Lee, Jeonghyun; Kim, Juyeop; Choi, Jaehyouk, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), pp.351 - 354, IEEE, 2021-09-13 |
| A 170MHz-Lock-In-Range and-253dB-FoM(jitter), 12-to-14.5GHz Subsampling PLL with a 150 mu W Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; et al, IEEE International Solid-State Circuits Conference (ISSCC), pp.280 - 282, IEEE, 2020-02-19 |
| A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.378 - 380, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk, 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, pp.94 - 97, Institute of Electrical and Electronics Engineers Inc., 2018-09-05 |
| A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells Kim, Mina; Choi, Seojin; Choi, Jaehyouk, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, pp.C142 - C143, Institute of Electrical and Electronics Engineers Inc., 2015-06-01 |
| A 45nm SOI-CMOS PLL with a wideband LC-VCO Lee, Kun-Seok; Beck, Sungho; Jeon, Hamhee; Yoon, Youngchang; Choi, Jaehyouk; Lee, Chang-Ho; Kenney, J. Stevenson, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, IEEE, 2011-11-01 |
| A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator Park, Suneui; Yoo, Seyeon; Shin, Yuhwan; Lee, Jeonghyun; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.212 - 214, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop Lee, Yongsun; Yoon, Heein; Kim, Mina; Choi, Jaehyouk, 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Institute of Electrical and Electronics Engineers Inc., 2016-06-15 |
| A robust latch-type sense amplifier using adaptive latch resistance Song, Taejoong; Lee, Sang Min; Choi, Jaehyouk; Kim, Stephen; Kim, Gyuhong; Lim, Kyutae; Laskar, Joy, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, pp.182 - 185, IEEE, 2010-06-02 |
| A-58dBc-Worst-Fractional-Spur and-234dB-FoM(jitter), 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word Seong, Taeho; Lee, Yongsun; Hwang, Chanwoong; Lee, Jeonghyun; Park, Hangi; Lee, Kyuho Jason; Choi, Jaehyouk, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.270 - 272, Institute of Electrical and Electronics Engineers Inc., 2020-02-19 |
| An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS Yoo, Seyeon; Park, Suneui; Choi, Seojin; Cho, Yoonseo; Yoon, Heein; Hwang, Chanwoong; Choi, Jaehyouk, 2021 IEEE International Solid- State Circuits Conference (ISSCC), IEEE, 2021-02-13 |
| An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate Lim, Younghyun; Lee, Jeonghyun; Park, Suneui; Choi, Jaehyouk, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp.299 - 300, IEEE, 2018-01-24 |
| An Ultra-Low Integrated-Phase-Noise 28-GHz LO Generator for 5G Transceivers Supporting Multiple Frequency Bands Yoon, Heein; Park, Suneui; Kim, Juyeop; Choi, Jaehyouk, 2022 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2022, pp.2 - 3, Institute of Electrical and Electronics Engineers Inc., 2022-08 |
| Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers Yoo, Seyeon; Choi, Seojin; Kim, Juyeop; Yoon, Heein; Lee, Yongsun; Choi, Jaehyouk, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp.303 - 304, IEEE, 2018-01-24 |
| Optimization of analog circuits via simulation and a Lagrangian-type gradient-based method Lim, Eunji; Kim, Youngmin; Choi, Jaehyouk, 2015 Winter Simulation Conference (WSC), pp.1206 - 1217, IEEE, 2015-12-09 |
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