A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC

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To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phase-error correction (FPEC) technique [1] is one promising architecture. By emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM), the FPEC PLL can achieve ultra-low jitter that is almost comparable to that of ILCMs. In addition, since the FPEC PLL has an integrator in its transfer function, it can also achieve a low reference spur and a high multiplication factor (N), which is different from ILCMs. However, the FPEC PLL of an analog implementation in [1] has difficulty maintaining optimal loop characteristics, which vary easily due to PVT variations or a change in the output frequency. To facilitate the calibration of loop characteristics, the FPEC can be implemented in an all-digital PLL (ADPLL), increasing the control word of a DCO, D
Publisher
Institute of Electrical and Electronics Engineers Inc.
Issue Date
2018-02-13
Language
English
Citation

65th IEEE International Solid-State Circuits Conference, ISSCC 2018, pp.396 - 398

DOI
10.1109/ISSCC.2018.8310351
URI
http://hdl.handle.net/10203/269592
Appears in Collection
RIMS Conference Papers
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