DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seong, Taeho | ko |
dc.contributor.author | Lee, Yongsun | ko |
dc.contributor.author | Yoo, Seyeon | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2019-12-13T12:30:07Z | - |
dc.date.available | 2019-12-13T12:30:07Z | - |
dc.date.created | 2019-11-19 | - |
dc.date.created | 2019-11-19 | - |
dc.date.issued | 2018-02-13 | - |
dc.identifier.citation | 65th IEEE International Solid-State Circuits Conference, ISSCC 2018, pp.396 - 398 | - |
dc.identifier.uri | http://hdl.handle.net/10203/269592 | - |
dc.description.abstract | To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phase-error correction (FPEC) technique [1] is one promising architecture. By emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM), the FPEC PLL can achieve ultra-low jitter that is almost comparable to that of ILCMs. In addition, since the FPEC PLL has an integrator in its transfer function, it can also achieve a low reference spur and a high multiplication factor (N), which is different from ILCMs. However, the FPEC PLL of an analog implementation in [1] has difficulty maintaining optimal loop characteristics, which vary easily due to PVT variations or a change in the output frequency. To facilitate the calibration of loop characteristics, the FPEC can be implemented in an all-digital PLL (ADPLL), increasing the control word of a DCO, D | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC | - |
dc.type | Conference | - |
dc.identifier.wosid | 000459205600163 | - |
dc.identifier.scopusid | 2-s2.0-85046418573 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 396 | - |
dc.citation.endingpage | 398 | - |
dc.citation.publicationname | 65th IEEE International Solid-State Circuits Conference, ISSCC 2018 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Francisco Marriott Marquis | - |
dc.identifier.doi | 10.1109/ISSCC.2018.8310351 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Seong, Taeho | - |
dc.contributor.nonIdAuthor | Lee, Yongsun | - |
dc.contributor.nonIdAuthor | Yoo, Seyeon | - |
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