A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC

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dc.contributor.authorSeong, Taehoko
dc.contributor.authorLee, Yongsunko
dc.contributor.authorYoo, Seyeonko
dc.contributor.authorChoi, Jaehyoukko
dc.date.accessioned2019-12-13T12:30:07Z-
dc.date.available2019-12-13T12:30:07Z-
dc.date.created2019-11-19-
dc.date.created2019-11-19-
dc.date.issued2018-02-13-
dc.identifier.citation65th IEEE International Solid-State Circuits Conference, ISSCC 2018, pp.396 - 398-
dc.identifier.urihttp://hdl.handle.net/10203/269592-
dc.description.abstractTo improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phase-error correction (FPEC) technique [1] is one promising architecture. By emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM), the FPEC PLL can achieve ultra-low jitter that is almost comparable to that of ILCMs. In addition, since the FPEC PLL has an integrator in its transfer function, it can also achieve a low reference spur and a high multiplication factor (N), which is different from ILCMs. However, the FPEC PLL of an analog implementation in [1] has difficulty maintaining optimal loop characteristics, which vary easily due to PVT variations or a change in the output frequency. To facilitate the calibration of loop characteristics, the FPEC can be implemented in an all-digital PLL (ADPLL), increasing the control word of a DCO, D-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleA -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC-
dc.typeConference-
dc.identifier.wosid000459205600163-
dc.identifier.scopusid2-s2.0-85046418573-
dc.type.rimsCONF-
dc.citation.beginningpage396-
dc.citation.endingpage398-
dc.citation.publicationname65th IEEE International Solid-State Circuits Conference, ISSCC 2018-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationSan Francisco Marriott Marquis-
dc.identifier.doi10.1109/ISSCC.2018.8310351-
dc.contributor.localauthorChoi, Jaehyouk-
dc.contributor.nonIdAuthorSeong, Taeho-
dc.contributor.nonIdAuthorLee, Yongsun-
dc.contributor.nonIdAuthorYoo, Seyeon-
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