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Choi, Jaehyouk (최재혁)
부교수, (전기및전자공학부)

http://icsl.kaist.ac.kr

Research Area
Analog ICs, RFICs, Mixed Signal ICs
Co-researchers
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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    A Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction

    Hwang, Chan woong; Park, Hangi; Lee, Yongsun; et al, IDEC Journal of Integrated Circuits and Systems, v.9, no.4, pp.37 - 43, 2023-10

    2
    Counter-Based Frequency Discriminator for Fine Dust Sensor

    박선의; 박한기; 김주엽; et al, IDEC Journal of Integrated Circuits and Systems, v.9, no.2, pp.42 - 46, 2023-04

    3
    A 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop

    조용우; 채문재; 최재혁, IDEC Journal of Integrated Circuits and Systems, v.9, no.1, pp.1 - 5, 2023-01

    4
    A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

    Park, Suneui; Yoo, Seyeon; Shin, Yuhwan; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.1, pp.78 - 89, 2023-01

    5
    A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

    Park, Hangi; Hwang, Chanwoong; Seong, Taeho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.12, pp.3527 - 3537, 2022-12

    6
    A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M

    Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2841 - 2855, 2022-09

    7
    An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector

    Park, Suneui; Choi, Seojin; Yoo, Seyeon; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2829 - 2840, 2022-09

    8
    A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

    Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.2, pp.480 - 491, 2022-02

    9
    Ultra-Low Power Quadrature LO-Generator

    신유환; 임영현; 박선의; et al, IDEC Journal of Integrated Circuits and Systems, v.8, no.1, pp.31 - 36, 2022-01

    10
    Frequency discriminator for the fine dust sensor

    박선의; 김주엽; 박한기; et al, IDEC Journal of Integrated Circuits and Systems, v.7, no.3, pp.19 - 24, 2021-07

    11
    A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator

    Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.1, pp.298 - 309, 2021-01

    12
    Design of a 12 to 14.5 GHz Digitally-Controlled Oscillator for an Ultra-Low-Jitter PLL

    방주은; 조용우; 최서진; et al, IDEC Journal of Integrated Circuits and Systems, v.7, no.1, pp.18 - 23, 2021-01

    13
    Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)

    Blaauw, David; Lee, Hoi; Keane, John P.; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.55, no.12, pp.3127 - 3130, 2020-12

    14
    A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method

    Choi, Se-Eun; Ahn, Hyunjin; Hur, Joonhoi; et al, ELECTRONICS, v.9, no.2, 2020-02

    15
    A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single VCO-Based Edge-Racing Time Quantizer

    Lee, Jeonghyun; Bang, Jooeun; Lim, Younghyun; et al, IEEE Solid-State Circuits Letters, v.2, no.12, pp.305 - 308, 2019-12

    16
    An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

    Kim, Juyeop; Lim, Younghyun; Yoon, Heein; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.12, pp.3466 - 3477, 2019-12

    17
    A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

    Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2501 - 2512, 2019-09

    18
    A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC

    Park, Suneui; Kim, Juyeop; Hwang, Chanwoong; et al, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.29, no.8, pp.548 - 550, 2019-08

    19
    A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration

    Yoon, Heein; Park, Suneui; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.6, pp.1564 - 1574, 2019-06

    20
    An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114

    Choi, Seojin; Yoo, Seyeon; Lee, Yongsun; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS , v.54, no.4, pp.927 - 936, 2019-04
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