Methods to detect and correct timing errors of oscillators are very important to achieve the low-jitter performance of a ring-DCO (RDCO) digital PLL (DPLL). A TDC is widely used to quantize these timing errors. The higher the resolution of a TDC, the lower the quantization noise becomes. However, such TDCs require large power to cover a sufficiently wide dynamic range. Instead, ,  presented jitter-minimization techniques that used a bang-bang phase detector (BBPD) and the background optimization of the proportional gain of the loop, KP (top left of Fig. 17.1.1). This approach is effective for low-power designs but is limited in reducing the output jitter, since the information of timing errors by the BBPD is just binary. To overcome this limit,  used three parallel BBPDs, each of which had a different time threshold, τ TH . While maintaining the optimal spacing between the τ TH S (instead of decreasing it unconditionally) along with the calibration of K P , the DPLL in  succeeded in decreasing the jitter. Despite these efforts, previous DPLLs - had a fundamental limit to minimizing the jitter since they optimized only K Pbased on an incorrect assumption that the RDCO jitter was “white” Gaussian while ignoring flicker noise. However, different from thermal noise, the energy of flicker noise is concentrated at low-frequency offsets near DC, and its effect appears as a random drift of the RDCO frequency over time . Thus, to suppress flicker noise and further reduce the overall jitter, the flicker-induced frequency drifts (f DS ) must be calibrated by adjusting the gain of the integral path, K 1 , as well as K P .