Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 11281 to 11300 of 51618
| Chip-level Wireless Power Transfer Scheme Design for Next Generation Wireless Interconnected Three-Dimensional Integrated Circuits Song, Jinwook; Jung, Seungtaek; Park, Shinyoung; Kim, Jonghoon; Hong, Seokwoo; Kim, Joungho, IEEE Wireless Power Transfer Conference (WPTC), IEEE Wireless Power Transfer Conference 2017, 2017-05-10 |
| Chip-level wireless power transfer scheme design using magnetic-field resonant coupling for next generation wireless interconnected 3-D IC = 차세대 무선 삼차원 반도체를 위한 자기장 공명 기술을 이용한 칩-단위 무선 전력 전송 도식 설계link Song, Jinwook; Kim, Joung Ho; et al, 한국과학기술원, 2018 |
| Chip-package co-design of power distribution network for system-in-package applications Kim, G.; Kam, D.G.; Chung, D.; Kim, Joungho, 6th Electronics Packaging Technology Conference, EPTC 2004, pp.499 - 501, IEEE, 2005-12-08 |
| Chip-package co-modeling & verification of noise coupling & generation in CMOS DC/DC buck converter Song, T.; Kim, J.; Pak, J.; Kim, Joungho, 20th International Zurich Symposium on Electromagnetic Compatibility, EMC Zurich 2009, pp.285 - 288, IEEE, 2009-01-12 |
| Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method Kim, Jae-Min; Lee, Woo-Jin; Shim, Yu-Jeong; Shim, Jong-Joo; Kim, Ki-Yeong; Pak, Jun-So; Kim, Joung-Ho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.33, no.3, pp.647 - 659, 2010-08 |
| Chip-package hybrid clock distribution network and DLL for low jitter clock delivery Daehyun Chung; Chunghyun Ryu; Hyungsoo Kim; Choonheung Lee; Jinhan Kim; Kicheol Bae; Jiheon Yu; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, no.1, pp.274 - 286, 2006-01 |
| Chip-Package Hybrid Clock Distribution Network and DLL for Low Jitter Clock Delivery Chung, Daehyun; Ryu, Chunghyun; Kim, Hyungsoo; Lee, Choonheung; Kim, Jinhan; Bae, Kicheol; Yu, Jiheon; et al, Solid-state circuits, IEEE Journal of, vol.41. pp. 274-286, 2006-01 |
| Chip-Package-Circuit Co-modeling for Analysis of Digital Power and Ground Noise Coupling Effect on CMOS Negative Feedback Operational Amplifier Kim, Joungho; Shim, Yujeong; Park, Jongbae, EMC compo, 2007 |
| Chip-scale high-speed Fourier-transform spectrometer based on a combination of a Michelson and a Fabry-Perot interferometer Yu, Kyoungsik; Park, N.; Lee, D.; Solgaard, O., Proceedings of IEEE Sensors, art. v.0, no.0, pp.412 - 415, IEEE, 2006 |
| Chip-scale wavelength standards(*) Bopp, Douglas G.; Hummon, Matthew T.; Kang, Songbai; Kitching, John; Li, Qing; Westly, Daron A.; Kim, Sangsik; et al, 7th International School of Physics "Enrico Fermi" on New Frontiers for Metrology: From Biology and Chemistry to Quantum and Data Science, pp.443 - 449, IOS Press BV, 2019-07 |
| CHIP-TO-CHIP INTERFACE USING MICROSTRIP CIRCUIT AND DIELECTRIC WAVEGUIDE Bae, Hyeon-Min; Song, Ha Il; Jin, Huxian |
| CHIP-TO-CHIP INTERFACE USING MICROSTRIP CIRCUIT AND DIELECTRIC WAVEGUIDE Bae, Hyeon-Min; Song, Ha Il; JIN HUXIAN |
| CHIP-TO-CHIP INTERFACE USING MICROSTRIP CIRCUIT AND DIELECTRIC WAVEGUIDE Bae, Hyeon-Min; Song, Ha Il; JIN HUXIAN |
| CHIP-TO-CHIP INTERFACE USING MICROSTRIP CIRCUIT AND DIELECTRIC WAVEGUIDE Bae, Hyeon-Min; Song, Ha Il; JIN HUXIAN |
| CHIP-TO-CHIP INTERFACE USING MICROSTRIP CIRCUIT AND DIELECTRIC WAVEGUIDE Bae, Hyeon-Min; Song, Ha Il; JIN HUXIAN |
| Chip-to-chip optical interconnect using direct optical wire bonding Rhee, Hyun-Woo; You, Jong Bum; Kim, Jaeyong; Yoon, Hyeonho; Kim, Myeongho; Kim, Chong Kook; Park, Hyo-Hoon, Conference on Optical Interconnects XXII at SPIE OPTO Conference, SPIE-INT SOC OPTICAL ENGINEERING, 2022-01 |
| Chip-to-chip optical link by using optical wiring method Cho, I.K.; Ahn, S.H.; Jeong, M.Y.; Rho, B.S.; Park, HyoHoon, Photonics: Design, Technology, and Packaging III, v.6801, pp.0 - 0, SPIE, 2007-12-05 |
| Chip-to-chip optical link system using an optical wiring method Cho, IK; Ahn, SH; Rho, BS; Chung, KS; Park, HyoHoon, IEEE PHOTONICS TECHNOLOGY LETTERS, v.19, no.13-16, pp.1151 - 1153, 2007-07 |
| Chip-to-chip vertical noise coupling from on-chip switching DC-DC converter to low noise amplifier in mixed-signal stacked 3D-IC = 혼성 모드 3차원 반도체 내의 온 칩 스위칭 모드 파워 서플라이에서 저잡음 증폭기로의 버티컬 노이즈 커플링link Koo, Kyoung-Choul; 구경철; et al, 한국과학기술원, 2012 |
| CHIP: Constraint Handling with Individual Penalty approach using a hybrid evolutionary algorithm Datta, Rituparna; Deb, Kalyanmoy; Kim, Jong-Hwan, NEURAL COMPUTING & APPLICATIONS, v.31, no.9, pp.5255 - 5271, 2019-09 |
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