Chip-Package Hybrid Clock Distribution Network and DLL for Low Jitter Clock Delivery

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This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.
Publisher
IEEE
Issue Date
2006-01
Keywords

chip-package hybrid clock distribution network; chip-package hybrid delay-locked loop dll

Citation

Solid-state circuits, IEEE Journal of, vol.41. pp. 274-286

ISSN
0018-9200
URI
http://hdl.handle.net/10203/577
Appears in Collection
EE-Conference Papers(학술회의논문)
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