Chip-level wireless power transfer scheme design using magnetic-field resonant coupling for next generation wireless interconnected 3-D IC

Abstract

The three-dimensional integrated circuit (3-D IC) stacking technology using the through silicon vias (TSV) and the silicon interposer has finally been applied to semiconductor packaging technology and open new paradigm for high-performance ending 2-D shrinking by Moore’s law. However, this 3-D semiconductor stacking requires expensive TSV processes and packaging techniques. As the number of vertically stacked dies by the so-called "Kim’s law" increases every year, it is predicted that it will be hard to accommodate the wired power delivery network for power supply of those dies within in an available area of the package. Therefore, in this thesis, we proposed a wireless power transfer (WPT) scheme using magnetic-field resonance coupling (MFRC) technology in 3-D IC to overcome the limitation of the conventional power transmission method using wired power distribution network. In addition, we analyze the proposed scheme by physically modeling the magnetic-field resonance coupling phenomenon and design the rectifier circuits for the proposed scheme using the CMOS process. Finally, we experimentally verified and validated the proposed MFRC-WPT scheme by operating the analog circuit designed on the chip with the rectifier circuits.