Browse "School of Electrical Engineering(전기및전자공학부)" bySubjectnanowire

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Computational Study on the Performance of Si Nanowire pMOSFETs Based on the k . p Method

Shin, Mincheolresearcher; Lee, S; Klimeck, G, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.57, no.9, pp.2274 - 2283, 2010-09

Demonstration of a piezoelectric energy harvester using laterally aligned $BaTiO_3$ nanowire arrays with extremely high aspect ratio = 긴 종횡 비의 횡 정렬된 $BaTiO_3$ 나노와이어 배열을 이용한 압전 에너지 수확 소자 구현link

Choi, So-Young; Yoon, Jun-Bo; et al, 한국과학기술원, 2015

Double-Gate Nanowire Field Effect Transistor for a Biosensor

Ahn, Jae-Hyuk; Choi, Sung-Jin; Han, Jin-Woo; Park, Tae-Jung; Lee, Sang-Yupresearcher; Choi, Yang-Kyuresearcher, NANO LETTERS, v.10, no.8, pp.2934 - 2938, 2010-08

Double-gate nanowire field effect transistor for a biosensor = Double-Gate 구조의 나노와이어 트랜지스터와 바이오센서 응용에 대한 연구link

Ahn, Jae-Hyuk; 안재혁; et al, 한국과학기술원, 2013

Eletrothermal analysis of poly-si nanowire and its application to localized annealing of gate-all-around field-effect transistor = 폴리실리콘 나노와이어의 전기적, 열적 특성분석 및 이를 바탕으로 한 트랜지스터에의 응용link

Park, Jun-Young; 박준영; et al, 한국과학기술원, 2016

Fabrication of Vertical Silicon Nanotube Array Using Spacer Patterning Technique and Metal-Assisted Chemical Etching

Jeong, Hyeon Ho; Lee, Junghyung; Bok, Cheolkyu; Lee, Seok-Heeresearcher; Yoo, Seunghyupresearcher, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.16, no.1, pp.130 - 134, 2017-01

High Aspect Ratio Silicon Nanowire for Stiction Immune Gate-All-Around MOSFETs

Han, Jin-Woo; Moon, Dong-Il; Choi, Yang-Kyuresearcher, IEEE ELECTRON DEVICE LETTERS, v.30, no.8, pp.864 - 866, 2009-08

High Throughput Ultralong (20 cm) Nanowire Fabrication Using a Wafer-Scale Nanograting Template

Yeon, Jeongho; Lee, Young Jae; Yoo, Dong Eun; Yoo, Kyoung Jong; Kim, Jin Su; Lee, Jun; Lee, Jeong Oen; et al, NANO LETTERS, v.13, no.9, pp.3978 - 3984, 2013-09

Hybrid Porphyrin-Silicon Nanowire Field-Effect Transistor by Opto-Electrical Excitation

Seol, Myeong-Lok; Choi, Sung-Jin; Choi, Ji-Min; Ahn, Jae-Hyuk; Choi, Yang-Kyuresearcher, ACS NANO, v.6, no.9, pp.7885 - 7892, 2012-09

Local Electro-Thermal Annealing for Repair of Total Ionizing Dose-Induced Damage in Gate-All-Around MOSFETs

Park, Jun-Young; Moon, Dong-Il; Bae, Hagyoul; Roh, Young Tak; Seol, Myeong-Lok; Lee, Byung-Hyun; Jeon, Chang-Hoon; et al, IEEE ELECTRON DEVICE LETTERS, v.37, no.7, pp.843 - 846, 2016-07

Localized Electrothermal Annealing with Nanowatt Power for a Silicon Nanowire Field-Effect Transistor

Park, Jun-Young; Lee, Byung-Hyun; Lee, Geon-Beom; Bae, Hagyoul; Choi, Yang-Kyuresearcher, ACS APPLIED MATERIALS & INTERFACES, v.10, no.5, pp.4838 - 4843, 2018-02

Multiple-gate CMOS thin-film transistor with polysilicon nanowire

Im, Mae-Soon; Han, Jin-Woo; Lee, Hyun-Jin; Yu, Lee-Eun; Kim, Sung-Ho; Kim, Chang-Hoon; Jeon, Sang-Cheol; et al, IEEE ELECTRON DEVICE LETTERS, v.29, no.1, pp.102 - 105, 2008-01

Nanowire FET Biosensors on a Bulk Silicon Substrate

Ahn, Jae-Hyuk; Kim, Jee-Yeon; Choi, Kyung-Yong; Moon, Dong-Il; Kim, Chang-Hoon; Seol, Myeong-Lok; Park, Tae-Jung; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.59, no.8, pp.2243 - 2249, 2012-08

Nonvolatile Memory by All-Around-Gate Junctionless Transistor Composed of Silicon Nanowire on Bulk Substrate

Choi, Sung-Jin; Moon, Dong-Il; Kim, Sung-Ho; Ahn, Jae-Hyuk; Lee, Jin-Seong; Kim, Jee-Yeon; Choi, Yang-Kyuresearcher, IEEE ELECTRON DEVICE LETTERS, v.32, no.5, pp.602 - 604, 2011-05

Quantum Simulation Study on Performance Optimization of GaSb/InAs nanowire Tunneling FET

Hur, Ji-Hyun; Jeon, Sanghunresearcher, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.5, pp.630 - 634, 2016-10

Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced From Hot-Carrier Injection

Park, Jun-Young; Moon, Dong-Il; Seol, Myeong-Lok; Kim, Choong-Ki; Jeon, Chang-Hoon; Bae, Hagyoul; Bang, Tewook; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.63, no.3, pp.910 - 915, 2016-03

Simulation Study of Germanium p-Type Nanowire Schottky Barrier MOSFETs

Lee, Jaehyun; Shin, Mincheolresearcher, IEEE ELECTRON DEVICE LETTERS, v.34, no.3, pp.342 - 344, 2013-03

Surface-Roughness-Limited Mean Free Path in Silicon Nanowire Field Effect Transistors

Jung, Hyo-Eun; Shin, Mincheolresearcher, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.60, no.6, pp.1861 - 1866, 2013-06

(The) study of band structure and transport of silicon nanowire with various cross sections using finite element method = FEM을 활용한 다양한 단면을 가진 실리콘 나노와이어의 밴드 구조와 전자수송에 대한 연구link

Park, Sangchun; Shin, Mincheol; et al, 한국과학기술원, 2017

Theoretical study of the surface roughness scattering effects on silicon nanowire FETs = 실리콘 나노와이어 트랜지스터에서의 표면 거칠기 충돌영향에 대한 이론연구link

Jung, Hyo-Eun; 정효은; et al, 한국과학기술원, 2013



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