Fabrication of Vertical Silicon Nanotube Array Using Spacer Patterning Technique and Metal-Assisted Chemical Etching

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We propose a process combining metal-assisted chemical etching and a spacer patterning technique to fabricate dense, vertical silicon nanotubes (SiNTs) with sub-60 nm wall thickness, which may have potential advantages for various devices. Moreover, we investigate the effect of the etch rate controlled by the mixture solution ratio to obtain SiNTs with ideal morphology. The fabricated high aspect ratio SiNTs exhibit good structural stability, leading to bundle-free arrays, which can be ideal for nanostructure-based suppression of optical reflection.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-01
Language
English
Article Type
Article
Keywords

THERMAL-CONDUCTIVITY; NANOWIRE ARRAYS; REDUCTION

Citation

IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.16, no.1, pp.130 - 134

ISSN
1536-125X
DOI
10.1109/TNANO.2016.2637911
URI
http://hdl.handle.net/10203/222779
Appears in Collection
EE-Journal Papers(저널논문)
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