Browse "EE-Journal Papers(저널논문)" by Subject jitter

Showing results 1 to 17 of 17

1
A 250-MHz-2-GHz wide-range delay-locked loop

Kim, BG; Kim, Lee-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, pp.1310 - 1321, 2005-06

2
A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

Lee, Woo-Jin; Kim, Jae-Min; Ryu, Chung-Hyun; Park, Jong-Bae; Kim, Jun-Chul; Kim, Joung-Ho, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.19, pp.512 - 514, 2009-08

3
A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2501 - 2512, 2019-09

4
A behavioral modeling approach to the design of a low jitter clock source

Manganaro, G; Kwak, SU; Cho, SeongHwan; Pulincherry, A, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.50, no.11, pp.804 - 814, 2003-11

5
A Compact and Wide-Band Passive Equalizer Design Using a Stub With Defected Ground Structure for High Speed Data Transmission

Shim, Yu-Jeong; Lee, Woo-Jin; Song, Eak-Hwan; Cho, Jeong-Hyeon; Kim, Joung-Ho, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.20, pp.256 - 258, 2010-05

6
A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

Kim, BG; Kim, Lee-Sup; Park, KI; Jun, YH; Cho, SI; Kim, LS; Jun, YH; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, pp.1522 - 1530, 2009-05

7
A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells

Kim, Mina; Choi, Seojin; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.2, pp.401 - 411, 2016-02

8
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration

Yoon, Heein; Park, Suneui; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.6, pp.1564 - 1574, 2019-06

9
A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

Choi, Seojin; Yoo, Seyeon; Lim, Younghyun; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1878 - 1889, 2016-08

10
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.2, pp.480 - 491, 2022-02

11
Adaptive cycle extension in multimedia document retrieval

Won, Youjip; Cho, K, XML-BASED DATA MANAGEMENT AND MULTIMEDIA ENGINEERING-EDBT 2002 WORKSHOPS, v.2490, pp.391 - 405, 2002-03

12
Adaptive cycle management in soft real-time disk retrieval

Won, Youjip; Shin, Il-Hoon; Koh, Kern, INFORMATION SYSTEMS, v.31, no.8, pp.832 - 848, 2006-12

13
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector

Park, Suneui; Choi, Seojin; Yoo, Seyeon; Cho, Yoonseo; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2829 - 2840, 2022-09

14
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114

Choi, Seojin; Yoo, Seyeon; Lee, Yongsun; Jo, Yongwoo; Lee, Jeonghyun; Lim, Younghyun; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS , v.54, no.4, pp.927 - 936, 2019-04

15
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.12, pp.3466 - 3477, 2019-12

16
An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-mu m CMOS

Lee, Junghyup; George, Arup K.; Je, Minkyu, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.55, no.9, pp.2489 - 2497, 2020-09

17
New Phase-Locked Loop Design: Understanding the Impact of a Phase-Tracking Channel Detector

Lee, Jaewook; Moon, Jaekyun; Zhang, Tong; Haratsch, Erich F., IEEE TRANSACTIONS ON MAGNETICS, v.46, no.3, pp.830 - 836, 2010-03

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