New Phase-Locked Loop Design: Understanding the Impact of a Phase-Tracking Channel Detector

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We consider design of a phase-locked loop (PLL) that runs in conjunction with a phase-compensating channel detector capable of tracking and compensating for slow-varying phase errors. The main significance of this highly nontraditional timing recovery structure is that unlike the traditional PLLs, the loop's overall tracking ability and the steady-state jitter performance can be controlled more or less separately. The effective bandwidth of the PLL is set much lower than the traditional PLL for given input phase error fluctuations. As a result, the PLL jitter is made considerably smaller than traditional systems. On the other hand, the tracking ability of the overall loop depends largely on the window parameter associated with the phase estimator operating inside the Viterbi-like trellis detector. The window parameter has only a small effect on the loop jitter. The new PLL design is tested via tracking speed, timing jitter and error rate performance comparisons against a timing recovery method based on traditional PLL design. Simulation results in a turbo equalizer setting are also presented that validate the new PLL design methodology proposed.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2010-03
Language
English
Article Type
Article
Keywords

TIMING RECOVERY

Citation

IEEE TRANSACTIONS ON MAGNETICS, v.46, no.3, pp.830 - 836

ISSN
0018-9464
DOI
10.1109/TMAG.2009.2035927
URI
http://hdl.handle.net/10203/99004
Appears in Collection
EE-Journal Papers(저널논문)
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