A 250-MHz-2-GHz wide-range delay-locked loop

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This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DILL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2005-06
Language
English
Article Type
Article
Keywords

PLL; SYSTEM

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, pp.1310 - 1321

ISSN
0018-9200
DOI
10.1109/JSSC.2005.848035
URI
http://hdl.handle.net/10203/86126
Appears in Collection
EE-Journal Papers(저널논문)
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