A behavioral modeling approach to the design of a low jitter clock source

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Designing a low-jitter clock synthesizer is not a trivial task. Multiple noise and disturbance sources combine together in the nonlinear blocks of the phased-lock loop (PLL) affecting its performance. Moreover, deceptively small circuit nonideal characteristics can have nonnegligible effects in the behavior of the whole system. A behavioral modeling approach allowing a systematic design of the PLL is discussed here. This approach allows the designer to maintain a grasp of the fundamentals using coarse models at the early stage of the design and to eventually gain insight on the lower order effects by gradually increasing the level of detail as the design develops. Moreover, accurate design specifications for the actual circuit blocks are obtained and, eventually the transistor-level results can be back-annotated into the behavioral model for further verification. This methodology is here demonstrated in the context of the modeling, design and the implementation of a fully integrated BiCMOS 1.76 ps rms jitter 180-MHz clock synthesizer. A detailed functional model including the crystal oscillator, the main circuit nonlinearities, and noise sources of the PLL is presented. The building blocks models development has been motivated by actual circuit implementations. Moreover, computational pitfalls have been identified and solutions have been proposed. Finally, the key behavioral model results have been compared against measured results obtained from an actual fabricated prototype validating the effectiveness of the proposed approach.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2003-11
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.50, no.11, pp.804 - 814

ISSN
1057-7130
DOI
10.1109/TCSII.2003.819134
URI
http://hdl.handle.net/10203/83533
Appears in Collection
EE-Journal Papers(저널논문)
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