Browse "EE-Conference Papers(학술회의논문)" by Author Jang, SA
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| Channel-width effect on hot-carrier degradation in NMOSFETs with recessed-LOCOS isolation structure Cho, Byung Jin; Yue, JMP; Chim, WK; Qin, WH; Chan, DSH; Kim, YB; Jang, SA, Proc. of the 7th International Symp. on the Physical and Failure Analysis of Integrated Circuits (I, pp.94 - 94, 1999-07-05 |
| Double spacer LOCOS process with shallow recess of silicon for 0.20 um isolation Cho, Byung Jin; Jang, SA; Song, TS; Pyi, SH; Kim, JC, International Conf. on Solid State Devices and Materials (SSDM), pp.40 - 40, 1996-08-26 |
| Sidewall-sealed double LOCOS isolation structure with defect-free isolation recess Cho, Byung Jin; Kim, YB; Jang, SA; Kim, JC, 43rd Spring Meeting of the Japan Society of Applied Physics and Related Societies, pp.730 - 730, 1996-03-28 |
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