Double spacer LOCOS process with shallow recess of silicon for 0.20 um isolationDouble spacer LOCOS process with shallow recess of silicon for 0.20 um isolation

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Issue Date
1996-08-26
Language
ENG
Citation

International Conf. on Solid State Devices and Materials (SSDM), pp.40 - 40

URI
http://hdl.handle.net/10203/119623
Appears in Collection
EE-Conference Papers(학술회의논문)
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