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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Double spacer LOCOS process with shallow recess of silicon for 0.20 um isolationDouble spacer LOCOS process with shallow recess of silicon for 0.20 um isolation

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dc.contributor.authorCho, Byung Jin-
dc.contributor.authorJang, SA-
dc.contributor.authorSong, TS-
dc.contributor.authorPyi, SH-
dc.contributor.authorKim, JC-
dc.date.accessioned2013-03-15T12:52:22Z-
dc.date.available2013-03-15T12:52:22Z-
dc.date.created2012-02-06-
dc.date.issued1996-08-26-
dc.identifier.citationInternational Conf. on Solid State Devices and Materials (SSDM), v., no., pp.40 - 40-
dc.identifier.urihttp://hdl.handle.net/10203/119623-
dc.languageENG-
dc.titleDouble spacer LOCOS process with shallow recess of silicon for 0.20 um isolation-
dc.title.alternativeDouble spacer LOCOS process with shallow recess of silicon for 0.20 um isolation-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage40-
dc.citation.endingpage40-
dc.citation.publicationnameInternational Conf. on Solid State Devices and Materials (SSDM)-
dc.identifier.conferencecountryJapan-
dc.identifier.conferencecountryJapan-
dc.contributor.localauthorCho, Byung Jin-
dc.contributor.nonIdAuthorJang, SA-
dc.contributor.nonIdAuthorSong, TS-
dc.contributor.nonIdAuthorPyi, SH-
dc.contributor.nonIdAuthorKim, JC-
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EE-Conference Papers(학술회의논문)
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