Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

Abstract

We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al2O3, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (Delta V-th) was 0V even after a PBS time (t(stress)) of 3000 s under a gate voltage (V-G) condition of 5V (with an electrical field of 1.25MV/cm). On the other hand, when the first GI was deposited by PEALD, the Delta V-th value of a-IGZO TFTs was 0.82V after undergoing an identical amount of PBS. In order to interpret the disparate Delta V-th values resulting from PBS quantitatively, the average oxide charge trap density (N-T) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher N-T resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of N-T near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface. Published by AIP Publishing.