Browse "School of Electrical Engineering(전기및전자공학부)" by Author Jang, SA
Showing results 1 to 7 of 7
| A mechanism of field-oxide-ungrowth phenomenon in recessed isolation process and practical solution Jang, SA; Kim, YB; Cho, Byung Jin; Kim, JC, JOURNAL OF THE ELECTROCHEMICAL SOCIETY, v.144, no.8, pp.2933 - 2940, 1997-08 |
| Channel-width effect on hot-carrier degradation in NMOSFETs with recessed-LOCOS isolation structure Cho, Byung Jin; Yue, JMP; Chim, WK; Qin, WH; Chan, DSH; Kim, YB; Jang, SA, Proc. of the 7th International Symp. on the Physical and Failure Analysis of Integrated Circuits (I, pp.94 - 94, 1999-07-05 |
| Double spacer LOCOS process with shallow recess of silicon for 0.20 um isolation Cho, Byung Jin; Jang, SA; Song, TS; Pyi, SH; Kim, JC, International Conf. on Solid State Devices and Materials (SSDM), pp.40 - 40, 1996-08-26 |
| Evaluation of double spacer local oxidation of silicon (LOCOS) isolation process for sub-quarter micron design rule Jang, SA; Kim, YB; Cho, Byung Jin; Kim, JC, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES REVIEW PAPERS, v.36, no.3B, pp.1433 - 1438, 1997-03 |
| Hot-carrier degradation mechanism in narrow- and wide-channel n-MOSFETs with recessed LOCOS isolation structure Yue, JMP; Chim, WK; Cho, Byung Jin; Chan, DSH; Qin, WH; Kim, YB; Jang, SA; et al, IEEE ELECTRON DEVICE LETTERS, v.21, no.3, pp.130 - 132, 2000-03 |
| Isolation process induced wafer warpage Jang, SA; Yeo, IS; Kim, YB; Cho, Byung Jin; Lee, SK, ELECTROCHEMICAL AND SOLID STATE LETTERS, v.1, no.1, pp.46 - 48, 1998-07 |
| Sidewall-sealed double LOCOS isolation structure with defect-free isolation recess Cho, Byung Jin; Kim, YB; Jang, SA; Kim, JC, 43rd Spring Meeting of the Japan Society of Applied Physics and Related Societies, pp.730 - 730, 1996-03-28 |
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