Browse "School of Electrical Engineering(전기및전자공학부)" by Author Chang, Dong-Jin
Showing results 1 to 12 of 12
| A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC Kim, Wan; Hong, Hyeok-Ki; Roh, Yi-Ju; Kang, Hyun-Wook; Hwang, Sun-Il; Jo, Dong Shin; Chang, Dong-Jin; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1826 - 1839, 2016-08 |
| A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration Chang, Dong-Jin; Choi, Michael; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.9, pp.2691 - 2700, 2021-09 |
| A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision Roh, Yi-Ju; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.2833 - 2837, 2020-12 |
| A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization Kim, Ye-Dam; Chung, Jae-Hyun; Lozada, Kent Edrian; Chang, Dong-Jin; Ryu, Seung-Tak, 17th IEEE Asian Solid-State Circuits Conference (A-SSCC) - Integrated Circuits and Systems for the Connection of Intelligent Things, IEEE, 2021-11-07 |
| A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration Chang, Dong-Jin; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.3, pp.281 - 285, 2018-03 |
| A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration Oh, Dong-Ryeol; 김종인; Jo, Dong-Shin; Kim, Woo-Cheol; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.1, pp.288 - 297, 2019-01 |
| A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks Seo, Min-Jae; Roh, Yi-Ju; Chang, Dong-Jin; Kim, Wan; Kim, Ye-Dam; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.12, pp.1904 - 1908, 2018-12 |
| A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye Dam; Kim, Jong-Pal; Chang, Dong-Jin; Lim, Won-Mook; Chung, Jaehyun; et al, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, pp.189 - 192, Institute of Electrical and Electronics Engineers Inc., 2019-11 |
| An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation Lim, Seung-Yong; Mabilangan, Raymond; Chang, Dong-Jin; Cho, Young-Jae; Choi, Michael; Ryu, Seung-Tak, 17th IEEE Asian Solid-State Circuits Conference (A-SSCC) - Integrated Circuits and Systems for the Connection of Intelligent Things, IEEE, 2021-11-07 |
| Calibration techniques for high resolution and high speed time-interleaved SAR ADCs = 고해상도 고속 시분할 연속 근사 구조 아날로그-디지털 변환기를 위한 보정 기법link Chang, Dong-Jin; Ryu, Seung-Tak; et al, 한국과학기술원, 2019 |
MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs Chang, Dong-Jin; Nam, Byeong-Gyu; Ryu, Seung-Tak, IEEE ACCESS, v.9, pp.117554 - 117564, 2021 |
| Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC Chang, Dong-Jin; Kim, Wan; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.2, pp.322 - 332, 2017-02 |
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