A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision

Cited 2 time in webofscience Cited 0 time in scopus
  • Hit : 44
  • Download : 0
A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The ADC core occupies a 0.0128-mm(2) area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2020-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.2833 - 2837

ISSN
1549-7747
DOI
10.1109/TCSII.2020.2981971
URI
http://hdl.handle.net/10203/280051
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 2 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0