A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration

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This brief presents a wide frequency-range synthesizable multiplying delay-locked-loop with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes output frequency that ranges from 80 kHz to 680 MHz. Owing to the synthesized finely controlled charge pump and phase detector with background offset calibration, the prototype clock generator achieves a 5.2 ps integrated RMS jitter at 680 MHz output while consuming 0.5 mW under a 1.2 V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-03
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.3, pp.281 - 285

ISSN
1549-7747
DOI
10.1109/TCSII.2017.2689029
URI
http://hdl.handle.net/10203/240921
Appears in Collection
EE-Journal Papers(저널논문)
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