Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 25601 to 25620 of 51620
| MiniCon: Automatic Enforcement of a Minimal Capability Set for Security-Enhanced Containers Kang, Haney; Kim, Jinwoo; Shin, Seungwon, IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS), pp.490 - 494, IEEE, 2021-04 |
| Minimal backlogging method for estimation of available bandwidth Nam, S.Y.; Kim, S.; Sung, Dan Keun, GLOBECOM'04 - IEEE Global Telecommunications Conference, v.3, pp.1469 - 1473, 2004-11-29 |
| Minimal design of multi-output static CMOS logic circuits using transistor sharing = 트랜지스터 공유를 이용하는 다출력 정적 CMOS 논리회로의 최소화 설계link Lee, Yun-Tae; 이윤태; et al, 한국과학기술원, 1994 |
| Minimal representation of speech signals for generation of emotion speech and human-robot interaction Lee H.; Bien, Zeung nam, 16th IEEE International Conference on Robot and Human Interactive Communication, RO-MAN, pp.137 - 140, 2007-08-26 |
| Minimally Invasive Mechanism Design: Distributed Covering with Carefully Chosen Advice Maria-Florina Balcan; Sara Krehbiel; Georgios Piliouras; Shin, Jinwoo, IEEE CDC, IEEE, 2012-12-10 |
| Minimally invasive probes for programmed microfluidic delivery of molecules in vivo McCall, Jordan G.; Jeong, Jae-Woong, CURRENT OPINION IN PHARMACOLOGY, v.36, pp.78 - 85, 2017-10 |
| Minimization of Cross-talk Effect on Thermally Actuated Organic Displays Choi, Yang-Kyu; Yarimaga, Oktay; Kim, Tae Won; Jung, Yun Kyung; Park, Hyun Gyu, ICMAP, 2008-08 |
| Minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics Shin, HC; Lee, JA; Kim, Lee-Sup, Proceedings of the 1998 IEEE International Conference on Computer Design, pp.286 - 291, 1998-10-05 |
| Minimizing Effect of Input Filter Capacitor in a Digital Boundary Conduction Mode Power Factor Corrector Based on Time-Domain Analysis Kim, Jong-Woo; Moon, Gun-Woo, IEEE TRANSACTIONS ON POWER ELECTRONICS, v.31, no.5, pp.3827 - 3836, 2016-05 |
| Minimizing Energy Consumption Through Traffic Offloading in HetNets With Two-Class Traffic Song, Yujae; Kong, Peng-Yong; Han, Youngnam, IEEE COMMUNICATIONS LETTERS, v.19, no.8, pp.1394 - 1397, 2015-08 |
| Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping Heo, S; Shin, Youngsoo, ISOCC, IEEE, 2007-10-16 |
| Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping Sewan Heo; Youngsoo Shin, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE , v.15, no.7, pp.215 - 220, 2007-12 |
| Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping = 플립플랍 비대칭화와 테크놀로지 매핑을 통한 순차회로의 누설전류 감소link Heo, Se-Wan; 허세완; et al, 한국과학기술원, 2007 |
| Minimizing leakage power in sequential circuits by using mixed $V_t$ Flip-Flops = 혼합 문턱전압 플립플랍을 이용한 순차 회로의 누설 전류 감소 기법link Kim, Jae-Hyun; 김재현; et al, 한국과학기술원, 2008 |
| Minimizing leakage power in sequential circuits by using mixed Vt flip-flops Kim, J.; Shin, Youngsoo, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, pp.797 - 802, 2007-11-04 |
| Minimizing Leakage Power of Sequential Circuits through Mixed-V-t Flip-Flops and Multi-V-t Combinational Gates Kim, Jaehyun; Oh, Chungki; Shin, Youngsoo, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.15, no.1, 2009-12 |
| Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles Wang, Y; Lin, X; Xie, Q; Chang, Naehyuck; Pedram, M, Design Automation and Test in Europe (DATE), European Design and Automation Association (EDAA), 2014-03-24 |
| Minimizing the Number of IGMP Report Messages for Receiver-Driven Layered Video Multicasting Newaz, S.H.S.; Bae, Y; Lee, J; Gyu, ML; Crespi, N.; Choi JunKyun, Vehicular Technology Conference (VTC Spring), 2011 IEEE 73rd, pp.1 - 5, 2011-05-18 |
| Minimizing transmit power for cooperative multicell system with massive MIMO Kang, Jinkyu; Kang, Joonhyuk; Lee, Namjeong; Lee, Byungmoo; Bang, Jongho, Consumer Communications and Networking Conference, IEEE, 2013-01-12 |
| Minimizing wakeup latency under rush-current constraint in power-gated circuits = 파워 게이팅이 적용된 회로에서 제한된 돌입 전류를 사용한 활성화 시간 최적화 기법link Kim, Sang-Min; 김상민; et al, 한국과학기술원, 2010 |
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