Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping

Abstract

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit techniques, such as power gating, reverse body bias, and so on, have been developed, they are not transparent to designers\` perspective. They require significant amount of designers\` input and/or are not aligned with traditional VLSI design process. In this thesis, we focus on technology mapping, which is usually the last step of logic synthesis that transforms register transfer level of circuits into a gate-level netlist. Instead of traditional cost function of delay and area, we use a probabilistic leakage as our cost during technology mapping. We consider pin reordering as the option in our mapping, in an effort to reduce the leakage. We also give a variety in our libraries through gate-length biasing, which increases the gate length of library gates but only slightly. Conventional technology mapping only considers combinational circuit, although sequential elements such as flip-flops and latches take appreciable proportion of total leakage in sequential circuits. In an effort to reduce the leakage of sequential elements, we propose a new flip-flop, which is constructed by taking conventional flip-flop and applying gate-length biasing to a subset of transistors in the flip-flop. The resultant flip-flop shows very skewed characteristics in terms of its leakage and its delay. This flip-flop is then exploited in our technology mapping process to reduce the leakage of flip-flops.