Minimizing wakeup latency under rush-current constraint in power-gated circuits파워 게이팅이 적용된 회로에서 제한된 돌입 전류를 사용한 활성화 시간 최적화 기법

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Power-gated circuits suffer from rush current when they wake up. The rush current is very large if all switch cells are turned on at the same time, even larger than maximum switching current, which forms the basis of power network design. The wakeup scheduling problem is to determine the time each switch cell is turned on (turn-on time) such that the total rush current is kept below the maximum rush current that is allowed and the wakeup delay is minimized. Since there are finite number of switch cells that can be scheduled, we propose to determine signal slew in addition to turn-on time, so that we attain a capability of fine-tuning the rush current. The determined slew and turn-on time are then accurately realized through a method to synthesize sleep signal network, which we also propose. The proposed algorithms are integrated into a complete design flow from a power-gated netlist down to layout. Experiments in 1.1 V, 45-nm technology demonstrate that the wakeup delay is reduced by 76% on average compared with 2-pass turn-on, which is widely used in industry, and by 14% compared with state-of-the-art scheduling method.
Advisors
Shin, Young-Sooresearcher신영수researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
419065/325007  / 020083084
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ vii, 36 p. ]

Keywords

rush current; power gating; wakeup scheduling; turnon time; 슬루; 돌입전류; 파워게이팅; 활성화 스케쥴링; slew

URI
http://hdl.handle.net/10203/36554
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=419065&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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