Minimizing Effect of Input Filter Capacitor in a Digital Boundary Conduction Mode Power Factor Corrector Based on Time-Domain Analysis

Conventional phase leading input current (PLIC) compensation techniques have focused on a continuous conduction mode (CCM) boost power factor corrector (PFC). In precedent studies, the causes of the PLIC have been investigated by analyzing the current control loop and the input impedance of a boost PFC. However, in a boundary conduction mode (BCM) boost PFC, the current flowing through the input filter capacitor becomes a main cause due to its large ripple current. Despite that, there has not been any effort to compensate the current in the input filter capacitor (IFC) in a BCM boost PFC. In this paper, a new digital control method is proposed to compensate PLIC in a BCM boost PFC, by minimizing the effect of the IFC. The proposed method uses only the derivative of the input voltage, without any additional component. Also, the proposed method improves the displacement factor, but does not affect the distortion factor, resulting in a high power quality in the entire input and output conditions. The derivation of the proposed method is presented based on time-domain analysis, and the effectiveness of the proposed method is experimentally verified with a 60-Hz, 90-230 V-rms input and 395-V/0.5-A output prototype.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-05
Language
English
Keywords

PHASE PFC CONVERTERS; SWITCHING FREQUENCY; COMPENSATION; DISTORTION; IMPEDANCE; LOSSES

Citation

IEEE TRANSACTIONS ON POWER ELECTRONICS, v.31, no.5, pp.3827 - 3836

ISSN
0885-8993
DOI
10.1109/TPEL.2015.2449318
URI
http://hdl.handle.net/10203/207586
Appears in Collection
EE-Journal Papers(저널논문)
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