Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 36841 to 36860 of 51050
| Three-dimensional solar steam generation device with additional non-photothermal evaporation Kim, Kwanghyun; Yu, Sunyoung; Kang, Se-Young; Ryu, Seung-Tak; Jang, Ji-Hyun, DESALINATION, v.469, 2019-11 |
| Three-dimensional volume image reconstruction with cone beam projections = 원추형 방사선 투영 정보를 이용한 3차원 영상 재구성link Min, Hyoung-Bok; 민형복; et al, 한국과학기술원, 1982 |
Three-dimensional, multifunctional neural interfaces for cortical spheroids and engineered assembloids Park, Yoonseok; Franz, Colin K.; Ryu, Hanjun; Luan, Haiwen; Cotton, Kristen Y.; Kim, Jong Uk; Chung, Ted S.; et al, SCIENCE ADVANCES, v.7, no.12, 2021-03 |
| Three-dimensionally patterned Ag-Pt alloy catalyst on planar Si photocathodes for photoelectrochemical H-2 evolution Lim, Sung Yul; Ha, Kyungyeon; Ha, Heonhak; Lee, Soo Youn; Jang, Min Seok; Choi, Mansoo; Chung, Taek Dong, PHYSICAL CHEMISTRY CHEMICAL PHYSICS, v.21, no.8, pp.4184 - 4192, 2019-01 |
| Three-electrode gas sensor system using CMOS interface IC = CMOS 인터페이스 IC 를 이용한 금속 산화물 기반 3-전극 가스센서 시스템link Park, Jeong-Ho; 박정호; et al, 한국과학기술원, 2017 |
| Three-Electrode Metal-Oxide Gas Sensor System With CMOS Interface IC Park, Jeong Ho; Park, Kwang Min; Kim, Tae-Wan; Shin, Seongheon; Park, Chong-Ook; Yoo, Hyung-Joun, IEEE SENSORS JOURNAL, v.17, no.3, pp.784 - 793, 2017-02 |
| Three-Level Capacitor Clamping Single Sustaining Driver With Dual Energy Recovery Path for Low Cost AC Plasma Display Panel Choi, SW; Moon, GunWoo, JOURNAL OF DISPLAY TECHNOLOGY, v.5, pp.398 - 407, 2009-10 |
| Three-level differential buffer for increasing noise margin in pseudo-differential signalling Ha, K. -S.; Kim, Lee-Sup; Bae, S. -J.; Park, K. -I.; Choi, J. S.; Jun, Y. -H., ELECTRONICS LETTERS, v.46, no.21, pp.1429 - 1430, 2010-10 |
| Three-level LLC SRC for high and wide input voltage applications Lee, Il Oun; Moon, GunWoo, Power Electronics and ECCE Asia (ICPE & ECCE), 2011 IEEE 8th International Conference on, pp.52 - 59, IEEE, 2011-05-30 |
| Three-Level Resonant Converter With Double Resonant Tanks for High-Input-Voltage Applications Lee, Il-Oun; Cho, Shin-young; Moon, Gun-Woo, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, v.59, no.9, pp.3450 - 3463, 2012-09 |
| Three-level space vector PWM in low index modulation region avoiding narrow pulse problem Liu, Hyo L.; Cho, Gyu-Hyeong, Proceedings of the 1993 IEEE 24th Annual Power Electronics Specialist Conference, pp.257 - 262, IEEE, 1993-06-20 |
| Three-level 의사공진형 PWM 컨버터 김재현; 이일운; 김영도; 김재국; 문건우, 2010년도 전력전자학술대회, pp.160 - 161, KIPE, 2010-07 |
| Three-Phase Boost-Converter Based PMIC for Thermal Electric Generator Application Tran-Dinh, Thinh; Pham, Hieu Minh; Vu, Tien-Lam; Pham-Nguyen, Loan; Lee, Sang-Gug, 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019, pp.205 - 208, Institute of Electrical and Electronics Engineers Inc., 2019-11 |
| Three-Phase Magnetic Field Design for Low EMI and EMF Automated Resonant Wireless Power Transfer Charger for UAV Kim, Joungho; Kim, Hongseok; Jung, Daniel H.; Yoon, Kibum; Cho,Yeonje; Kong, Sunkyu; Kwack, Younghwan, IEEE Wireless Power Transfer Conference 2015, IEEE Wireless Power Transfer Conference 2015, 2015-05-13 |
| Three-phase wireless power transfer system and three-phase wireless chargeable unmanned aerial vehicle system based on the same Kim, Joungho; Song, Chi-Uk, 2018-09-25 |
| Three-stage clos-network switch architecture with buffered center stage for multi-class traffic Kang, MK; Kyung, Chong-Min, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.15, pp.263 - 276, 2006-04 |
| Three-stage clos-network switch architecture with buffered center stage for multi-class traffic = 다중 계층의 트래픽을 위한 버퍼형 중간단을 가진 삼단 Clos 네트워크 스위치link Kang, Moo-Kyung; 강무경; et al, 한국과학기술원, 2006 |
| Three-stage model for robust real-time face tracking Do, Jun-Hyeong; Bien, Zeung nam, INTERNATIONAL JOURNAL OF IMAGING SYSTEMS AND TECHNOLOGY, v.17, no.6, pp.321 - 327, 2007 |
| Three-STEP HEURISTIC ALGORITHM FOR OPTIMAL PLA COLUMN FOLDING YANG, YY; Kyung, Chong-Min, ELECTRONICS LETTERS, v.24, no.17, pp.1088 - 1090, 1988-08 |
| Three-STEP PIN ASSIGNMENT ALGORITHM FOR BUILDING BLOCK LAYOUT CHOI, SG; Kyung, Chong-Min, ELECTRONICS LETTERS, v.28, no.20, pp.1882 - 1884, 1992-09 |
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