Three-stage clos-network switch architecture with buffered center stage for multi-class traffic

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Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue does not completely remove the blocking in the buffered modules under multi-class traffic. In this paper, we propose a competition-free memory-memory-memory (CFM3) switch which is a three-stage Clos-network switch with buffered center stage. The CFM3 deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, CFM3 is free from reordering problem due to simple control mechanism. Simulation result shows the delay of the proposed CFM3 switch closely approaches that of the ideal Output Queued switch under multi-class traffic when strict priority policy popularly used for class-based switch is deployed. The CFM3 achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch records about 77% throughput.
Publisher
WORLD SCIENTIFIC PUBL CO PTE LTD
Issue Date
2006-04
Language
English
Article Type
Article
Keywords

NONBLOCKING

Citation

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.15, pp.263 - 276

ISSN
0218-1266
DOI
10.1142/S0218126606003088
URI
http://hdl.handle.net/10203/91405
Appears in Collection
EE-Journal Papers(저널논문)
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